Senior Digital Engineer

Silicon Laboratories International Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

Medical & dental insurance

Bi-annual health screening

Office above Tai Seng MRT

Job summary

Silicon Laboratories International Pte Ltd in Singapore is seeking a Design Engineer to join our Silicon Engineering team, driving the design, implementation, and optimization of cutting-edge SoCs through advanced physical design methodologies.

The successful candidate will work across RTL handoff to GDSII, define floorplanning and CTS strategies, optimize power, performance and area, and collaborate with front-end, verification, DFT, and packaging teams to ensure smooth tape-out readiness.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or related field.
• 4+ years of experience in ASIC physical design.
• Hands-on expertise in EDA tools: Synopsys (ICC2, Fusion Compiler, PrimeTime)
• Cadence (Innovus, Tempus), or equivalent.
• Strong background in timing analysis, low-power methodologies, and ECO flows.
• Solid understanding of architecture-to-GDSII flows and sign-off requirements.
• Experience with chip-level integration and hierarchical design methodologies.
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS).
• Familiarity with DFT, STA, and physical verification methodologies.
• Exposure to multi-clock, multi-voltage, and multi-domain designs
• Excellent problem-solving and communication skills.

Responsibilities

• Execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).
• Define and drive floorplanning, clock-tree synthesis (CTS), placement, routing, and timing closure strategies.
• Own and optimize power, performance, and area (PPA) metrics for assigned designs.
• Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS).
• Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration.
• Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability.
• Mentor and guide junior engineers, fostering technical growth and design excellence.
• Work closely with foundries and vendors on process technology bring-up, PDK updates, and tape-out readiness.

Skills

Physical design

Floorplanning

CTS

Placement & routing

Timing closure

PPA optimization

Sign-off flows

DFT/STA

Collaboration

Mentoring

Foundry/PDK coordination

Education

Electrical Engineering / VLSI degree

Tools

Synopsys ICC2

Fusion Compiler

PrimeTime

Cadence Innovus

Cadence Tempus

Job description

What we’re looking for:

We are seeking a highly skilled Design Engineer to join our Silicon Engineering team. This role involves driving the design, implementation, and optimization of cutting-edge SoCs through advanced physical design methodologies. The ideal candidate will have deep expertise in synthesis, floorplanning, place-and-route, timing closure, power/performance optimization, and sign-off flows.

Skills you’ll need:

• Execute the end-to-end physical design flow for complex SoCs and IP blocks (from RTL handoff to GDSII).
• Define and drive floorplanning, clock-tree synthesis (CTS), placement, routing, and timing closure strategies.
• Own and optimize power, performance, and area (PPA) metrics for assigned designs.
• Manage design constraints, synthesis strategies, and sign-off criteria (timing, IR drop, EM, DRC/LVS).
• Collaborate with front-end RTL, DFT, verification, and packaging teams to ensure seamless integration.
• Drive EDA tool flow automation and methodology enhancements for improved efficiency and scalability.
• Mentor and guide junior engineers, fostering technical growth and design excellence.
• Work closely with foundries and vendors on process technology bring-up, PDK updates, and tape-out readiness.

Education and/or Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or related field.
• 4+ years of experience in ASIC physical design
• Hands-on expertise in EDA tools: Synopsys (ICC2, Fusion Compiler, PrimeTime),
• Cadence (Innovus, Tempus), or equivalent.
• Strong background in timing analysis, low-power methodologies, and ECO flows.
• Solid understanding of architecture-to-GDSII flows and sign-off requirements.
• Experience with chip-level integration and hierarchical design methodologies.
• Knowledge of low-power design techniques (UPF/CPF, power gating, DVFS).
• Familiarity with DFT, STA, and physical verification methodologies.
• Exposure to multi-clock, multi-voltage, and multi-domain designs
• Excellent problem-solving and communication skills.

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Medical and dental insurance coverage including spouse and child(ren)
• Bi yearly health screening and flu vaccination
• Office location is above Tai Seng MRT station