SOC Design Engineer

MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED seeks an experienced IC design engineer to join our SoC/FPGA team in Singapore. You will contribute to RTL design, verification, and tape-out readiness for multi-gate SoCs while addressing low power constraints.

You should hold a Bachelor or Master in Electrical/Electronics Engineering with an IC design focus and have DSM node experience (65/45/40/28/16nm). Strong communication and ability to work in a multi-cultural team are essential.

Qualifications

• Bachelor or Master in Electrical/Electronics Engineering with IC design emphasis.
• Experience in DSM SoC design, verification and tape-out across multiple nodes.
• Experience in one or more of GPS, WLAN, BT, NFC, Ethernet, SoC/ARM/AHB bus design is a plus.
• Expert knowledge of Low power methods and UPF/CPF.
• Experience through IC life cycle from conception to silicon validation.
• Able to work in a multi-cultural team with a strong drive to excel.
• Good written and communication skills.

Responsibilities

• Design digital logic with high-level description language (VHDL/Verilog) from specification
• Design quality RTL that meets all design requirements of input/output, constraints, multi clock domains, functional modes, and analog blocks
• Design RTL with Low power requirement from standard power intent file input
• Design RTL for SoC and FPGA-friendly and DFT compliant code is critical
• Design RTL for IP development and SoC assembly
• Design RTL for SoC Clock & Reset structures is a plus
• Verify the design through extensive test-bench simulation and ability to debug with FPGA prototyping
• Experience with Design For Test requirement is a plus
• Experience with Synthesis, and Logic Equivalent checks are added advantage
• Work with other RTL2netlist and Backend team to resolve any design issues

Skills

IC design

Low power design

Verbal and written communication

Team collaboration

Education

Electrical/Electronics Engineering (Bachelors/Masters)

Job description

Job Responsibilities

• Design digital logic with high-level description language (VHDL/Verilog) from specification
• Design quality RTL that meets all design requirement of input/output requirements, constraints, multiple clock domains, functional modes, and analog blocks
• Design RTL with Low power requirement from standard power intent file input
• Design of RTL for SoC and FPGA-friendly and DFT compliant code is critical
• Design of RTL for IP development and SoC assembly
• Design of RTL for SoC Clock & Reset structures is a plus
• Verify the design through extensive test-bench simulation and ability to debug with FPGA prototyping
• Experience with Design For Test requirement is a plus
• Experience with Synthesis, and Logic Equivalent checks are added advantage
• Work with other RTL2netlist and Backend team to resolve any design issues

Job Requirements

• Bachelor Degree/Master's in Electrical/Electronics Engineering with an emphasis in IC design
• Experience in the complete cycle of DSM (65, 45, 40, 28, 16nm) SoC Design, verification and tape-out experience of several million-gates-count complex SoC together with validation of silicon is essential
• Previous development experience in one or more of these areas: GPS, WLAN, BT, NFC, Ethernet, SoC/ARM/AHB bus design is a plus
• Expert knowledge of Low power input standard like UPF/CPF and SoC connectivity tools e.g. Core Consultant, etc. has a strong advantage
• Experience through IC life cycle from conception, design, verification, tapeout and silicon validation
• Able to work in a multi-cultural team with a strong drive to excel
• Able to work independently on a given assignment and work hard to finish on time
• Good written and communication skills

Location: Next to Bendemeer MRT