Senior DFT Engineer - Low-Power SoC & MBIST

ambiq micro singapore private ltd.; Singapore; On-site; SGD 120,000 - 170,000; Full time

Job summary

ambiq micro singapore private ltd. is seeking a senior DFT engineer to lead scan insertion, ATPG, and MBIST for ultra-low power SoCs. The role emphasizes low-power DFT architectures, test coverage optimization, and collaboration with design and test teams.

The candidate should have 5+ years in DFT, strong RTL knowledge, and experience with Tcl scripting. Excellent English communication is required for cross-continental collaboration in a fast-moving hardware company.

Qualifications

• BS/MS in ECE/EE with at least 5 years of DFT experience.
• Experience with scan (Stuck-At, At-Speed, Path-Delay) and MBIST.
• Experience creating hierarchical DFT architecture for complex SoCs.
• Experience in Low-Power DFT and MBIST.
• Experience in test time and test coverage analysis for scan and MBIST patterns.
• Experience with production test programs and collaboration with test engineers.
• Strong timing concepts and constraint development knowledge.
• Experience developing RTL-based DFT test benches.
• Scripting with Tcl preferred.
• Gate-level simulation GLS preferred.
• Self-motivated, detail-oriented, strong English communication.

Responsibilities

• Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
• Develop and implement low-power DFT architecture and infrastructure.
• Generate structural test vectors, analyse, and improve coverage, test time and test cost.
• Perform pre/post-layout scan and MBIST simulations.
• Work with designers on STA, physical, power and logical issues related to DFT.
• Work with test engineers to bring up test vectors on silicon.

Skills

DFT implementation

Boundary scan

MBIST

ATPG

Low-power DFT

RTL

Tcl scripting

GLS

Team collaboration

English communication

Education

BS/MS in ECE/EE

Tools

EDA tools

Job description

ambiq micro singapore private ltd. is seeking a senior DFT engineer to lead scan insertion, ATPG, and MBIST for ultra-low power SoCs. The role emphasizes low-power DFT architectures, test coverage optimization, and collaboration with design and test teams.

The candidate should have 5+ years in DFT, strong RTL knowledge, and experience with Tcl scripting. Excellent English communication is required for cross-continental collaboration in a fast-moving hardware company.