Senior ASIC Design Engineer

black sesame technologies (singapore) pte ltd; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

black sesame technologies (singapore) pte ltd is seeking a talented engineer to join our core team in designing next-generation AI compute engines. You will implement high-efficiency logic modules and ensure designs meet rigorous timing requirements. Candidates should possess a strong background in RTL, timing analysis, and low-power techniques.

This role requires deep technical knowledge in hardware fundamentals and proficiency in SystemVerilog and Verilog. Join us and contribute to cutting-edge AI technology!

Qualifications

• Deep understanding of CMOS logic, Setup/Hold time, Skew/Jitter.
• Familiarity with Static Timing Analysis and path delays.
• Strong coding skills in SystemVerilog/Verilog focusing on synthesizable code.
• Understanding of pipelining, stalling, and bypass logic.

Responsibilities

• Implement high-efficiency logic modules using SystemVerilog/Verilog.
• Analyze and fix timing violations to ensure target frequency.
• Apply basic low-power techniques and analyze their impact.
• Run Lint, CDC, and RDC checks for silicon behavior.
• Collaborate with physical design team on congestion and timing.

Skills

RTL Design

Timing Analysis

Low Power Techniques

Backend Collaboration

Python

TCL

Education

BS/MS/PhD in Electrical Engineering or Computer Engineering

Tools

SystemVerilog

Verilog

Job description

Position Overview:

In this role, you will be part of the core team designing our next-generation AI compute engines. You will go beyond high-level RTL, diving into the fundamental hardware constraints that make high-performance AI silicon possible. You will focus on optimizing high-speed datapath logic while ensuring the design meets rigorous timing and power requirements.

Responsibilities:

• RTL Design: Implement high-efficiency logic modules using SystemVerilog/Verilog, focusing on AI-specific ALU and datapath components.
• STA & Timing: Analyze and fix timing violations (Setup/Hold) to ensure the design closes at target frequencies.
• Low Power & PPA: Apply basic low-power techniques (e.g., Clock Gating) and analyze their impact on PPA.
• Design Sign-off: Run Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure robust silicon behavior.
• Backend Collaboration: Work closely with the physical design team to understand and resolve congestion and timing issues.

Qualification/ Requirements:

• Education: BS/MS/PhD in Electrical Engineering or Computer Engineering.
• Hardware Fundamentals: Deep understanding of CMOS logic, Setup/Hold time, Skew/Jitter, and the impact of PVT (Process, Voltage, Temperature) corners.
• STA Knowledge: Familiar with the concept of Static Timing Analysis, including path delays, false paths, and multi-cycle paths.
• HDL Proficiency: Strong coding skills in SystemVerilog/Verilog with an emphasis on synthesizable code and hardware-oriented thinking.
• Digital Architecture: Understanding of pipelining, stalling, and bypass logic in high-performance datapaths.
• ing: Proficiency in Python, Shell, or TCL (essential for EDA tool interaction).

Preferred Skills:

• ASIC Flow Experience: Familiarity with the industry-standard ASIC design flow (from RTL to GDSII).
• ALU/Math Foundations: Knowledge of computer arithmetic (Fixed-point, IEEE-754) and its hardware implementation.
• Advanced CDC: Experience handling complex asynchronous interfaces and synchronization techniques.
• RISC-V Exposure: Understanding of RISC-V ISA and its pipeline stages.