Senior ASIC Implementation Engineer (Synthesis & STA)

black sesame technologies (singapore) pte ltd; Singapore; On-site; SGD 120,000 - 170,000; Full time

Job summary

Black Sesame Technologies (Singapore) Pte Ltd is seeking a Senior ASIC Implementation Engineer (Synthesis & STA) to drive high-performance AI cores and ADAS IP through synthesis, low-power implementation, and timing closure. You will collaborate with physical design, floorplanning, and SoC teams to optimize PPA while delivering complex IP blocks.

You will leverage Verilog/SystemVerilog, Synopsys tools, and UPF flows to ensure robust RTL, timing accuracy, and scalable design methodologies across

Qualifications

• Strong knowledge of digital design and VLSI concepts.
• Experience with Verilog and SystemVerilog in production environments.
• Hands-on with synthesis tools and static timing analysis.
• Familiarity with low-power design flows and formal verification tools.

Responsibilities

• Lead synthesis and optimization for IP blocks focusing on PPA.
• Collaborate with physical design on floorplanning, placement, routing, timing closure.
• Work with SoC teams on clock, reset, timing, and power requirements.
• Develop and maintain synthesis, formal verification, and STA flows.
• Support delivery of multiple complex IP blocks and integration into SoC flows.
• Identify RTL improvements to boost frequency, power, and convergence.
• Suggest design methodology enhancements and automation ideas.

Skills

Verilog

SystemVerilog

Digital design

VLSI concepts

Tcl

Python

RTL optimization

Synthesis

Timing analysis

Education

Bachelor's/Master's/Ph.D. in Electrical/Computer Engineering or related field

Tools

Synopsys Design Compiler

Synopsys PrimeTime

Cadence Conformal LEC

Synopsys Formality

UPF-based low-power design

Job description

Position Overview:

As a Senior ASIC Implementation Engineer (Synthesis & STA) within our Core IP Design Team, you will contribute to the development and production of next-generation, high-performance, power-efficient AI cores and ADAS chips.

This is a highly visible role responsible for synthesis, low-power implementation, timing closure, and close collaboration with physical design and SoC teams. You will play an important role in optimizing our designs for performance, power, and area while helping bring complex products to market efficiently.

Responsibilities:

• Lead synthesis and optimization efforts for IP cores, with a focus on performance, power, and area (PPA).


• Collaborate with the physical design team on floorplanning, placement, routing, and timing closure.


• Work closely with the SoC team on clock, reset, timing, and power-related design requirements.


• Develop, maintain, and enhance synthesis, formal verification, and static timing analysis flows.


• Support the implementation and delivery of multiple complex IP blocks.


• Partner with SoC implementation engineers to integrate IP-level solutions into SoC-level design flows.


• Analyze implementation results and provide recommendations to improve RTL for higher frequency, lower power, and better physical design convergence.


• Identify opportunities to improve design methodologies, automation, and overall engineering efficiency.

Qualification/ Requirements:

• Education: Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.


• At least 3 years of relevant industry experience.


• Solid understanding of digital design and VLSI concepts.


• Proficiency in Verilog and SystemVerilog.


• Hands-on experience with synthesis tools, particularly Synopsys Design Compiler.


• Hands-on experience with static timing analysis using Synopsys PrimeTime.


• Experience with UPF-based low-power design and implementation flows.


• Experience with formal equivalence verification tools such as Cadence Conformal LEC and/or Synopsys Formality.


• Proficiency in ing languages such as Tcl, Perl, and Python.


• Strong analytical, problem-solving, and communication skills.


• Excellent attention to detail and a strong willingness to learn.

Preferred Skills:

• Experience implementing large-scale, high-frequency digital designs operating above 1 GHz.


• Experience with physical synthesis and physically aware optimization.


• Strong understanding of physical design concepts, including floorplanning, placement, clock-tree synthesis, routing, and timing closure.


• Ability to review RTL and recommend improvements for timing, power, area, and physical implementation.


• Experience developing AI accelerators, neural-network processors, or other high-performance compute chips.