Logic Design & Verification Engineer (RTL / UVM / ASIC Development)

DADACONSULTANTS PTE. LTD.; Singapore; On-site; SGD 60,000 - 90,000; Full time

Benefits offered by this job

Opportunity to work on advanced ASIC/SoC projects

Clear career progression in chip design and verification

Job summary

DADACONSULTANTS PTE. LTD. is seeking a front-end engineer in Singapore to work on high-performance chip systems. The role focuses on designing RTL modules and developing verification plans for ASIC/SoC projects. Candidates should have a strong foundation in digital design, familiarity with Verilog/SystemVerilog, and be enthusiastic about real-world applications in chip development.

The position offers clear career progression in a collaborative environment that emphasizes both design and verification.

Qualifications

• Bachelor’s degree or above in Electrical Engineering, Computer Engineering, or related fields.
• Understanding of digital design fundamentals and IC development flow.
• Familiarity with Verilog/SystemVerilog and basic RTL design concepts.

Responsibilities

• Design and implement RTL modules using Verilog/SystemVerilog for ASIC/SoC projects.
• Develop and execute verification plans, including testbench development using UVM methodology.
• Perform functional verification, debugging, and coverage analysis to ensure design correctness.

Skills

Verilog/SystemVerilog

UVM Methodology

Python

Scripting

Digital design fundamentals

Education

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Computer Engineering

Job description

My Client

My client is a fast-growing global technology company building high-performance chip systems for large-scale computing applications. The engineering team focuses on digital front-end design and verification, delivering robust and scalable ASIC solutions. The team works in a highly collaborative and engineering-driven environment, combining RTL design, verification methodologies, and system-level optimization. They are currently expanding their front-end engineering team to support next-generation chip development.

Job Responsibilities

• Design and implement RTL modules using Verilog/SystemVerilog for ASIC/SoC projects.
• Develop and execute verification plans, including testbench development using UVM methodology.
• Perform functional verification, debugging, and coverage analysis to ensure design correctness.
• Participate in SoC integration, testability (DFT) design, and overall front-end development flow.
• Collaborate with architecture, physical design, and software teams to ensure seamless integration.
• Contribute to automation and tooling improvements using scripting languages.

Job Requirements

• Bachelor’s degree or above in Electrical Engineering, Computer Engineering, or related fields.
• Understanding of digital design fundamentals and IC development flow.
• Familiarity with Verilog/SystemVerilog and basic RTL design concepts.
• Exposure to verification methodologies (e.g., UVM) is a plus.
• Basic scripting skills (Python / Shell) preferred.
• Strong analytical thinking, problem-solving ability, and learning agility.

What They Offer

• Opportunity to work on advanced ASIC/SoC projects with real-world impact.
• Exposure to both design and verification in a full front-end flow.
• Clear career progression in chip design and verification domains.