Senior Analog/Mixed-Signal Circuit Design Engineer (PLL/VCO)

Brightecs Innovation Pte Ltd; Singapore; On-site; SGD 120,000 - 160,000; Full time

Job summary

Brightecs Innovation Pte. Ltd. (BIP) in Singapore seeks a senior RFIC/PLL engineer to lead advanced CMOS PLL architecture, layout, and verification.

You will drive architecture choices, calibrations, and testing to achieve sub-100 fs jitter and wide tuning ranges with robust PVT behavior. The role emphasizes device-level design, layout leadership, and chip verification, leveraging LabView/Python/MATLAB for automation and data analysis.

Qualifications

• Bachelor, Master or PhD in Electronic Engineering, Micro-electronics or related field.
• 8+ years of relevant semiconductor experience.
• Experience with RF/mixed-signal lab equipment: high BW oscilloscope, signal source, VNA, spectrum analyzer, PN tester and probe station.
• Deep knowledge of phase noise, jitter, VCO push/pull, power-supply sensitivity, LO leakage and spur mechanisms.
• Proficiency in Python, MATLAB and SKILL scripting for data analytics and testing automation.

Responsibilities

• Define advanced CMOS PLL architecture at device level, drive verification and architecture decisions.
• Lead layout implementation, testing, and matching strategies to reduce noise and jitter.
• Achieve industry-leading jitter, noise, and spur performance; design calibration and testing engines.
• Design and verify key components: LC VCO, PFD, CP, LDO; perform system-level design and verification.
• Coordinate chip verification, tuning, and IP reuse; document design specs and test plans.

Skills

Python

MATLAB

Scripting

Data analytics

Testing automation

Education

Bachelor/Master/PhD in Electronic Engineering or Micro-electronics

Tools

High BW oscilloscope

Signal source

VNA

Spectrum analyzer

PN tester

Probe station

Job description

Brightecs Innovation Pte. Ltd. (BIP) in Singapore seeks a senior RFIC/PLL engineer to lead advanced CMOS PLL architecture, layout, and verification.

You will drive architecture choices, calibrations, and testing to achieve sub-100 fs jitter and wide tuning ranges with robust PVT behavior. The role emphasizes device-level design, layout leadership, and chip verification, leveraging LabView/Python/MATLAB for automation and data analysis.