Senior Analog/Mixed-Signal IC Layout Architect

Astera Labs; Singapore; Sur place; SGD 120 000 - 180 000; Plein temps

Résumé du poste

Astera Labs in Singapore is seeking a Senior Analog Mixed-Signal IC Layout Engineer to join our ASIC team. You will work on high-performance compute and networking standards in advanced CMOS, focusing on design, verification, and validation of real-world systems.

Requirements include BS/MS in EE/CS, RTL languages Verilog/SystemVerilog, UVM, Python/C/C++, and experience with PCIe, DDR, HBM or Serdes. Curiosity and a strong learning mindset are essential.

Qualifications

• Hands-on with RTL design languages and verification.
• Familiarity with UVM, functional coverage and assertions.
• Experience with Python, Perl, and C/C++ is desirable.

Responsabilités

• Design and/ or verification of blocks using leading edge methods and tools.

Connaissances

Verilog

SystemVerilog

UVM

Python

C/C++

Serdes

VLSI design

Computer Architecture

Formation

Bachelor's or Master's in EE/CS

Outils

Synopsys EDA tools

Description du poste

Astera Labs in Singapore is seeking a Senior Analog Mixed-Signal IC Layout Engineer to join our ASIC team. You will work on high-performance compute and networking standards in advanced CMOS, focusing on design, verification, and validation of real-world systems.

Requirements include BS/MS in EE/CS, RTL languages Verilog/SystemVerilog, UVM, Python/C/C++, and experience with PCIe, DDR, HBM or Serdes. Curiosity and a strong learning mindset are essential.