Staff Analog Mixed-Signal Circuit Design Engineer

Brightecs Innovation Pte Ltd; Singapore; On-site; SGD 120,000 - 160,000; Full time

Job summary

Brightecs Innovation Pte. Ltd. (BIP) in Singapore seeks a senior RFIC/PLL engineer to lead advanced CMOS PLL architecture, layout, and verification.

You will drive architecture choices, calibrations, and testing to achieve sub-100 fs jitter and wide tuning ranges with robust PVT behavior. The role emphasizes device-level design, layout leadership, and chip verification, leveraging LabView/Python/MATLAB for automation and data analysis.

Qualifications

• Bachelor, Master or PhD in Electronic Engineering, Micro-electronics or related field.
• 8+ years of relevant semiconductor experience.
• Experience with RF/mixed-signal lab equipment: high BW oscilloscope, signal source, VNA, spectrum analyzer, PN tester and probe station.
• Deep knowledge of phase noise, jitter, VCO push/pull, power-supply sensitivity, LO leakage and spur mechanisms.
• Proficiency in Python, MATLAB and SKILL scripting for data analytics and testing automation.

Responsibilities

• Define advanced CMOS PLL architecture at device level, drive verification and architecture decisions.
• Lead layout implementation, testing, and matching strategies to reduce noise and jitter.
• Achieve industry-leading jitter, noise, and spur performance; design calibration and testing engines.
• Design and verify key components: LC VCO, PFD, CP, LDO; perform system-level design and verification.
• Coordinate chip verification, tuning, and IP reuse; document design specs and test plans.

Skills

Python

MATLAB

Scripting

Data analytics

Testing automation

Education

Bachelor/Master/PhD in Electronic Engineering or Micro-electronics

Tools

High BW oscilloscope

Signal source

VNA

Spectrum analyzer

PN tester

Probe station

Job description

1. Advanced CMOS PLL architecture definition, device level design and verification.

3. Lead layout implementation and testing.

4. Achieve industry leading jitter, noise and spur performance.

5. Architecture and system level design.

• Architecture choice-based noise/jitter/spur spec (optimal architecture - integer/Fraction/SS/MDLL etc.)
• Derive system parameters (Loop BW, Noise margin, noise TF, spur reduction), system verification through behavioral to transistor model (Verilog-A, MATLAB, SpectreRF.
• Design and verify key components: LC VCO, R-VCO, MMD, PFD, CP, LF, frac-N SDM, calibration engine and LDO.
• Noise optimization (sub 100fs RMS jitter), wide tuning range (multi-GHz), low power and PVT robustness.
• Calibration logic (ADC based VCO gain tracking, background spur reduction, DTC linearization).

7. Layout and physical implementation.

• Lead layout floor planning, strategize noise reduciton through guardring, sensitive nodes, shielding.
• Layout best practices - matching, isolation.
• EMIR.

8. Chip verification and tuning.

• Automation using LabView, Python. PN, jitter, lock time, spur, temp sensitivity analysis through oscilloscope, spectrum analyzer, signal source and PN analyzer.

9. Documentation and IP Re-use.

• Authoring design spec, test plan, results report and app note.
• PLL IP solution package including behavioral model, PDK and testing platform.

Required Qualifications:

• Bachelors / Masters / Phd Degree in Electronic Engineering, Micro-electronics or a related field.
• With more than 8 years relevant experience in similar field in semiconductor industry.
• Skilled RF/mixed-signal lab equipment: high BW oscilloscope, signal source and VNA, spectrum analyzer, PN tester and probe station.
• Deep understanding of phase noise, jitter, VCO push/pull, power supply sensitivity, LO leakage and spur mechanisms.
• Python, MATLAB, SKILL scripting data analytics and testing automation skills.

About Us

Brightecs Innovation Pte. Ltd. (BIP) is a private limited company incorporated in Singapore, founded in September 2025. As a newly established, technology-oriented startup, our core business is currently focused on silicon IP for intelligent computing.

At the core of our operations is our R&D center, Superam Academy of Semiconductor Research (Superam), a fabless chip research institution also based in Singapore. It specializes in high-end semiconductor IP services, offering diverse IP solutions and standard cell libraries for advanced CMOS technologies by employing Design-Technology-Co-Optimization (DTCO) technology. We enable our customers to achieve full optimization of Power, Performance, and Area (PPA) when designing on foundries' unique processes.

As our business continues to grow, BIP is committed to expanding its capabilities and scope into broader areas of technology innovation. We invite talented professionals to join us on this exciting journey. For more company information, please visit www.bipsuperam.com.

Why Join BIP

At BIP, you will be a founding contributor to something extraordinary. We are a young, passionate team driven by curiosity and a shared ambition to push the boundaries of technology. Here, your ideas matter, your contributions are visible, and your growth is limited only by your ambition. As we expand into new frontiers, we invite you to grow with us, take on challenges that inspire you, and help shape the future from day one.