Senior Analog Design Engineer: Precision IPs ASIC Serdes

Trulyyy; Singapore; On-site; SGD 60,000 - 120,000; Full time

Job summary

Trulyyy in Singapore is seeking an Analog Designer to define specifications and execute transistor-level design for critical analog building blocks.

You will perform pre- and post-layout verification and work closely with layout engineers on device matching, shielding, and floorplanning sign-off. A strong background in LDO/BGR/POR or precision clock generation with Cadence Virtuoso is essential.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or equivalent with hands-on analog IP experience.
• Experience driving custom analog IPs from specification to tape-out.
• Strong background in power management (LDO, BGR, POR) or precision clock generation using Cadence Virtuoso.

Responsibilities

• Define specifications and perform transistor-level design for analog building blocks.
• Conduct pre- and post-layout verification.
• Collaborate with layout engineers on device matching, shielding, and floorplanning sign-off.

Skills

Analog IP design

Transistor-level design

Pre-layout verification

Floorplanning

Device matching

Sign-off procedures

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Virtuoso

SPICE

Job description

Trulyyy in Singapore is seeking an Analog Designer to define specifications and execute transistor-level design for critical analog building blocks.

You will perform pre- and post-layout verification and work closely with layout engineers on device matching, shielding, and floorplanning sign-off. A strong background in LDO/BGR/POR or precision clock generation with Cadence Virtuoso is essential.