Senior Analog/Mixed-Signal ASIC Layout Engineer

asteralabs; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Astera Labs, listed on NASDAQ as ALAB, is hiring an Analog / Mixed-Signal Layout Engineer to join our ASIC team in Singapore. You will contribute to design and verification of blocks in advanced CMOS nodes, focusing on high-performance compute and networking interfaces.

The ideal candidate has a hardware background in VLSI or Computer Architecture, hands-on RTL experience with Verilog/SystemVerilog, UVM, and scripting in Python or Perl, plus familiarity with PCIe, DDR, HBM, and Serdes.

Qualifications

• Pursuing BS or MS in EE/CS or related fields.
• Hardware engineering background with an emphasis in VLSI or Computer Architecture.
• Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.
• Hands-on knowledge of RTL design languages and Verilog, SystemVerilog.
• Familiarity with verification methodologies like UVM, functional coverage, assertions.
• Familiarity with scripting languages Python, Perl etc and hands-on experience in C/C++.

Responsibilities

• Design and/or verification of blocks using leading edge methodology and tools.
• Work on high‑speed interfaces such as PCIe, DDR, HBM and Serdes.

Skills

Verilog

SystemVerilog

UVM

Python

Perl

C/C++

RTL design

Education

BS in EE/CS

MS in EE/CS

Tools

Synopsys EDA tools

Job description

Astera Labs, listed on NASDAQ as ALAB, is hiring an Analog / Mixed-Signal Layout Engineer to join our ASIC team in Singapore. You will contribute to design and verification of blocks in advanced CMOS nodes, focusing on high-performance compute and networking interfaces.

The ideal candidate has a hardware background in VLSI or Computer Architecture, hands-on RTL experience with Verilog/SystemVerilog, UVM, and scripting in Python or Perl, plus familiarity with PCIe, DDR, HBM, and Serdes.