Tech Lead, Analog & Mixed-Signal IC Layout

Astera Labs; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Astera Labs in Singapore seeks a Tech Lead Analog Mixed-Signal IC Layout Engineer for the ASIC team, focusing on high-performance compute and networking in advanced CMOS nodes. You will design and verify blocks with Verilog/SystemVerilog, UVM, and related methodologies, collaborating across teams to deliver robust, scalable solutions.

The role requires hands-on hardware engineering in VLSI/Computer Architecture, experience with high-speed interfaces, and familiarity with Synopsys EDA tools.

Qualifications

• Hands-on knowledge of RTL design languages and tools including Verilog, SystemVerilog.
• Familiarity with verification methodologies like UVM, functional coverage, assertions.
• Familiarity with scripting languages Python, Perl and hands-on experience in C/C++.

Responsibilities

• Design and/or verification of blocks using leading edge methodology and tools.

Skills

Verilog/SystemVerilog

UVM

Python

C/C++

Digital design/verification

VLSI/Computer Architecture

Education

BS or MS in EE/CS or related fields

Tools

Synopsys EDA tools

RTL design tools (Verilog/SystemVerilog)

Job description

Astera Labs in Singapore seeks a Tech Lead Analog Mixed-Signal IC Layout Engineer for the ASIC team, focusing on high-performance compute and networking in advanced CMOS nodes. You will design and verify blocks with Verilog/SystemVerilog, UVM, and related methodologies, collaborating across teams to deliver robust, scalable solutions.

The role requires hands-on hardware engineering in VLSI/Computer Architecture, experience with high-speed interfaces, and familiarity with Synopsys EDA tools.