Lead Analog/Mixed-Signal IC Layout for High-Perf ASICs

asteralabs; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Astera Labs (NASDAQ: ALAB) is hiring an Analog / Mixed-Signal Layout Engineer to join its ASIC team, advancing high-performance compute and networking in advanced CMOS nodes. The ideal candidate has a hardware background with emphasis in VLSI/Computer Architecture and hands-on RTL design or verification experience.

The role requires familiarity with Verilog/SystemVerilog, UVM, and scripting (Python/Perl) with C/C++ alongside exposure to PCIe, DDR, HBM, and Serdes interfaces.

Qualifications

• Pursuing BS or MS in EE/CS or related fields.
• Hardware engineering background with emphasis in VLSI or Computer Architecture.
• Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.

Responsibilities

• Design and/or verification of blocks using leading edge methodology and tools.
• Work on analog/mixed-signal layout within ASIC team for high-performance compute and networking.
• Collaborate with hardware and software teams to validate real-world systems.

Skills

Verilog

SystemVerilog

UVM

Assertions

Python

Perl

C/C++

Digital design

RTL design

Functional coverage

Education

BS or MS in EE/CS

Tools

Synopsys EDA

Job description

Astera Labs (NASDAQ: ALAB) is hiring an Analog / Mixed-Signal Layout Engineer to join its ASIC team, advancing high-performance compute and networking in advanced CMOS nodes. The ideal candidate has a hardware background with emphasis in VLSI/Computer Architecture and hands-on RTL design or verification experience.

The role requires familiarity with Verilog/SystemVerilog, UVM, and scripting (Python/Perl) with C/C++ alongside exposure to PCIe, DDR, HBM, and Serdes interfaces.