Analog Design Engineer

CURIOUS TEK PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

CURIOUS TEK PTE. LTD. seeks an experienced engineer for design and implementation of mixed-signal CMOS IP. The role covers the full development cycle from circuit design to bench characterization, with emphasis on high-speed Serdes and analog layouts.

Candidates should have a Bachelor's in Microelectronics or related field and 5+ years in analog design, plus strong SPICE tool experience and familiarity with Cadence Spectre, Synopsys Custom Compiler, and Calibre.

Qualifications

• Bachelor or above degree in Microelectronic or Electronic and Information Engineering.
• 5+ years of experience in analog design.
• Strong knowledge of high-speed Serdes (PLL, CDR, CTLE/DFE, TX driver).

Responsibilities

• Design and implementation of mixed signal CMOS IP across development cycles, including circuit design, simulation, modeling, verification and bench characterization.
• Manage products utilizing leading-edge sub-micron CMOS technologies (e.g., 5/6nm).
• Develop state-of-the-art high-speed mixed-signal IP products (op amps, comparators, bandgap, LDOs, ADCs, DC-DC, Gbps Serdes TX/RX).

Skills

Analog design

Serdes knowledge

SPICE tools

Education

Bachelor or above in Microelectronic or Electronic and Information Engineering

Tools

Cadence Spectre

Synopsys Custom Compiler

Calibre

Job description

Job Responsibilities:

• Design and implementation of mixed signal CMOS IP. Development cycle including circuit design, simulation, modeling, verification and bench characterization.


• Management products utilizing leading edge sub-micron CMOS technologies, e.g., 5/6nm


• Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate (Gbps) Serdes TX/RX.

Requirements:

• Bachelor or above degree in Microelectronic or Electronic and Information Engineering


• 5 years or above experience in the area of analog design


• Good knowledge in analog IC design in high speed Serdes, e.g., PLL, CDR, CTLE/DFE, TX driver etc.


• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations


• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)


• Strong Communication skills, high level of independence, self-motivation and good team player