Senior / Analog Layout Engineer

AUREXIS TECH PTE. LTD.; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

AUREXIS TECH PTE. LTD. is seeking a circuit-layout engineer in Singapore with 3+ years of experience to design and own layouts for analog, digital and mixed-signal circuits. You will collaborate with analog designers on floorplanning and layout implementation, performing comprehensive DRC/LVS/ERc/ESD checks and ensuring timely milestones.

Proficiency in Cadence Virtuoso and Mentor Calibre is required, along with strong communication and teamwork skills to drive critical IP blocks to completion.

Qualifications

• Degree in Electrical/Electronics/Computer Engineering with at least 3 years of relevant experience.
• Must have knowledge of CMOS circuit theory.
• Solid experience in analog layout design.
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre.
• Experience in LVS, DRC, ERC, ANT, ESD, latch-up, EMIR and Reliability.
• Good understanding of signal and clock shielding and isolation techniques.
• Good communication skill and team player.

Responsibilities

• Design layout for analog, digital and mixed-signal circuits.
• Own layout of major custom IP blocks.
• Work closely with analog designers on floorplanning and layout implementation.
• Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
• Review resource deliverables and ensure quality/milestone completion.
• Plan schedules and drive assigned blocks to meet project timelines.

Skills

CMOS circuit theory

Analog layout design

Layout verification

Signal integrity

Team collaboration

Education

Degree in Electrical/ Electronics/ Computer Engineering

Tools

Cadence Virtuoso

Mentor Calibre

Job description

Main Responsibilities

• Design layout for analog, digital and mixed-signal circuits.
• Own layout of major custom IP blocks.
• Work closely with analog designers on floorplanning and layout implementation.
• Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
• Review resource deliverables and ensure quality/milestone completion.
• Plan schedules and drive assigned blocks to meet project timelines.

Main Requirements

• Degree in Electrical/ Electronics/ Computer Engineering or equivalent with minimum 3 years of relevant experiences.
• Must have knowledge of CMOS circuit theory
• Solid experience in analog layout design
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Good understanding of signal and clock shielding and isolation techniques
• Good communication skill and team player