RISC-V Hardware Crypto Architect – AES/ASCON Acceleration

Nanyang Technological University; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

NTU Singapore, a leading research-intensive university, seeks a Research Associate to integrate Hardware AES and ASCON accelerators into the RISC-V CVA6 core. You will work on memory-mapped interfaces or custom instructions, aligning toolchains for compiler and assembler support, and ensure proper integration into the ISA extension path.

The role requires a strong background in RISC-V, HDL RTL design, and FPGA prototyping, with emphasis on verification, testing, and performance optimization

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience with RISC-V architecture and custom instruction extensions.
• Proficiency in HDL languages and RTL design (Verilog/VHDL/SystemVerilog).

Responsibilities

• Design and implement Hardware AES and ASCON accelerators within the RISC-V CVA6 core.
• Define and implement custom RISC-V instructions to use the accelerators.
• Perform simulations to evaluate performance, latency, and throughput.

Skills

RISC-V architecture

Custom instruction extensions

HDL design (Verilog/VHDL/SystemVerilog

RTL design

FPGA prototyping

Education

Master’s degree in Electrical Engineering or Computer Engineering

Tools

GCC toolchain

LLVM toolchain

Vivado

Quartus

Job description

NTU Singapore, a leading research-intensive university, seeks a Research Associate to integrate Hardware AES and ASCON accelerators into the RISC-V CVA6 core. You will work on memory-mapped interfaces or custom instructions, aligning toolchains for compiler and assembler support, and ensure proper integration into the ISA extension path.

The role requires a strong background in RISC-V, HDL RTL design, and FPGA prototyping, with emphasis on verification, testing, and performance optimization