Secure FPGA Design & Verification Specialist (RISC-V)

TUM CREATE LIMITED; Singapore; On-site; SGD 60,000 - 90,000; Full time

Benefits offered by this job

Medical insurance

Leave days

Gym and facilities on campus

Competitive salary

Job summary

TUM CREATE LIMITED is seeking a Research Fellow/Associate/Engineer to join the QUASAR project, focusing on secure FPGA-based system development with RISC-V platforms. Emphasis on RTL design, verification, and bring-up, ideal for hardware verification and open-source hardware enthusiasts.

Role is a fixed-term contract until March 2029, with supervision in an international, interdisciplinary research setting and a competitive salary in Singapore.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• A strong foundation in digital design (RTL, timing, pipelining).
• Hands-on experience with FPGA design flows and RISC-V SoCs.
• Familiarity with Linux-based embedded systems and debugging tools.

Responsibilities

• FPGA System bring-up & validation for CVA6-based SoCs on FPGA (Genesys 2).
• Verification workflows: simulation and FPGA-based validation of RISC-V systems.
• Hardware security verification and analysis for post-quantum platform features.
• Automation: Python/TCL scripts for build, regression, and results analysis.

Skills

RTL

FPGA design

RISC-V

C/C++

Python

Linux

JTAG

Education

Bachelor/Master in Electrical Engineering / Computer Engineering / Computer Science

Tools

Vivado

Verilator

Job description

TUM CREATE LIMITED is seeking a Research Fellow/Associate/Engineer to join the QUASAR project, focusing on secure FPGA-based system development with RISC-V platforms. Emphasis on RTL design, verification, and bring-up, ideal for hardware verification and open-source hardware enthusiasts.

Role is a fixed-term contract until March 2029, with supervision in an international, interdisciplinary research setting and a competitive salary in Singapore.