Research Engineer, Gen-AI & In-Memory Computing

National University of Singapore; Singapore; On-site; SGD 52,000 - 78,000; Full time

Job summary

The National University of Singapore invites applications for a Research Engineer position in the OUTSMART Corp Lab under Professor Massimo Alioto, within the Department of Electrical and Computer Engineering. The role focuses on experimental validation and circuit exploration of near-PCM and in-memory SRAM computing macros.

The selected candidate will work on test structures, dataflow adaptation, chiplet interfaces, and final testchips in single and multi-chiplet configurations.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• Knowledge of circuit architectures and transistor-level design.
• Experience with silicon chip design and EDA tools.
• Ability to work independently and in a team.
• Good communication and interpersonal skills.
• Open to fixed-term contract.

Responsibilities

• Explore near-PCM and in-memory SRAM computing macros.
• Experimentally validate computing and memory macros and dataflow adaptation.
• Validate test structures with dataflow adaptation in single chip with high memory-logic interspersion.
• Validate chiplet interfaces and synchronization with memory-logic aggregation across chiplets.
• Validate final testchip in single- and multi-chiplet arrangements.
• Validate final testchip in single-chiplet arrangement.

Skills

Circuit architectures

Transistor-level design

Silicon chip design

EDA tools

Team collaboration

Communications

Education

Bachelor’s degree in Electrical Engineering

Tools

EDA tools

Job description

The National University of Singapore invites applications for a Research Engineer position in the OUTSMART Corp Lab under Professor Massimo Alioto, within the Department of Electrical and Computer Engineering. The role focuses on experimental validation and circuit exploration of near-PCM and in-memory SRAM computing macros.

The selected candidate will work on test structures, dataflow adaptation, chiplet interfaces, and final testchips in single and multi-chiplet configurations.