Memory Verification Engineer, Foundation IP & AI

Broadcom Singapore Pte Ltd

Singapore

On-site

SGD 120,000 - 180,000

Full time

8 days ago

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Job summary

Broadcom Singapore Pte Ltd is seeking a Foundation IP Memory Verification Engineer to join the Central Engineering Group in Singapore. The role involves validating memory macros, memory compilers and advanced AI memory components on latest process tech.

You will perform functional verification, SI/EM/IR analyses, transistor-level simulations for timing, power margins and reliability, plus develop scripts to automate the verification flow and support silicon debug activities.

Qualifications

  • Bachelor's degree in Electronics or Computer Engineering.
  • Minimum 2 years of relevant memory verification experience.
  • Strong understanding of transistor-level circuit behavior.

Responsibilities

  • Contribute to memory design validation of custom memory macros and memory compilers.
  • Perform functional verification and root-cause analysis of design discrepancies.
  • Conduct signal integrity analysis and propose design improvements.
  • Run transistor-level simulations to check Power Up/Lock Up issues and resolve them.
  • Perform EM/IR analysis and evaluate impact on timing and margins.
  • Develop scripts to automate verification flow and data analysis.
  • Support silicon debugs and correlate to spice models.
  • Collaborate with memory designers to improve validation flow.
  • Coordinate with leads to define and execute memory validation plan.

Education

Bachelor Electronics or computer engineering

Tools

SPICE simulators
EDA tools

Job description

Broadcom Singapore Pte Ltd is seeking a Foundation IP Memory Verification Engineer to join the Central Engineering Group in Singapore. The role involves validating memory macros, memory compilers and advanced AI memory components on latest process tech.

You will perform functional verification, SI/EM/IR analyses, transistor-level simulations for timing, power margins and reliability, plus develop scripts to automate the verification flow and support silicon debug activities.

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