Research Engineer (Gen-AI)

National University of Singapore; Singapore; On-site; SGD 52,000 - 78,000; Full time

Job summary

The National University of Singapore invites applications for a Research Engineer position in the OUTSMART Corp Lab under Professor Massimo Alioto, within the Department of Electrical and Computer Engineering. The role focuses on experimental validation and circuit exploration of near-PCM and in-memory SRAM computing macros.

The selected candidate will work on test structures, dataflow adaptation, chiplet interfaces, and final testchips in single and multi-chiplet configurations.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• Knowledge of circuit architectures and transistor-level design.
• Experience with silicon chip design and EDA tools.
• Ability to work independently and in a team.
• Good communication and interpersonal skills.
• Open to fixed-term contract.

Responsibilities

• Explore near-PCM and in-memory SRAM computing macros.
• Experimentally validate computing and memory macros and dataflow adaptation.
• Validate test structures with dataflow adaptation in single chip with high memory-logic interspersion.
• Validate chiplet interfaces and synchronization with memory-logic aggregation across chiplets.
• Validate final testchip in single- and multi-chiplet arrangements.
• Validate final testchip in single-chiplet arrangement.

Skills

Circuit architectures

Transistor-level design

Silicon chip design

EDA tools

Team collaboration

Communications

Education

Bachelor’s degree in Electrical Engineering

Tools

EDA tools

Job description

We are looking for a Research Engineer for the OUTSMART Corp Lab led by Professor Massimo Alioto, at the Department of Electrical and Computer Engineering, National University of Singapore (NUS).

The selected candidate is expected to:

• circuit exploration of near-PCM and in-memory SRAM computing macros, and related models
• experimental validation of computing and memory macros and their support of similarity/confidence-based computation skipping, and dataflow adaptation
• experimental validation of test structures with dataflow adaptation in single chip, high memory-logic interspersion
• experimental validation of chiplet interfaces and synchronization, test structures with final memory-logic aggregation, and dataflow adaptation across chiplets
• experimental validation of final testchip in single- and many-chiplet arrangement
• experimental validation of final testchip in single-chiplet arrangement

The appointment can commence immediately with a 1-year contract, with prospect of extension. Salary will be commensurate with qualifications and experience.

Qualifications

The candidate must possess:

• Minimally a Bachelor’s degree in either Electrical Engineering or strictly related (e.g., Computer, Electronics, Communication, or Information Engineering).
• Knowledge on circuit architectures, transistor-level design.
• Knowledge on silicon chip design, EDA tools.
• Ability to work independently and collaboratively in a team environment.
• Good communication and interpersonal skills.
• open to fixed term contract.