Research Fellow (Gen-AI)

National University of Singapore; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

The National University of Singapore (NUS) invites applications for a Research Fellow in the OUTSMART Corp Lab led by Professor Massimo Alioto within the Department of Electrical and Computer Engineering.

The fellow will explore near-PCM and in-memory SRAM computing macros, validate computing/memory macros, and contribute to dataflow adaptations and chiplet interfaces. The appointment is a 1-year contract with potential extension, starting immediately.

Qualifications

• PhD in Electrical Engineering or related field is required.
• Experience with circuit architectures and transistor-level design.
• Experience with silicon chip design and EDA tools.
• Ability to work independently and in teams; good communication.
• Open to fixed-term contract.

Responsibilities

• Experimentally validate near-PCM and in-memory SRAM computing macros.
• Validate computing and memory macros and their dataflow adaptation.
• Validate test structures with dataflow adaptation across chiplets.
• Validate final testchip in single- and multi-chiplet arrangements.
• Author high-quality research papers and present findings at international conferences.
• Manage technical milestones and guide PhD and master’s students.

Skills

Circuit architectures

Transistor-level design

Team collaboration

Communication skills

Fixed-term contract

Education

PhD in Electrical Engineering or related

Tools

EDA tools

Job description

Job Description

We are looking for a Research Fellow for the OUTSMART Corp Lab led by Professor Massimo Alioto, at the Department of Electrical and Computer Engineering, National University of Singapore (NUS).

The selected candidate is expected to:

• circuit exploration of near-PCM and in-memory SRAM computing macros, and related models
• experimental validation of computing and memory macros and their support of similarity/confidence-based computation skipping, and dataflow adaptation
• experimental validation of test structures with dataflow adaptation in single chip, high memory-logic interspersion
• experimental validation of chiplet interfaces and synchronization, test structures with final memory-logic aggregation, and dataflow adaptation across chiplets
• experimental validation of final testchip in single- and many-chiplet arrangement
• experimental validation of final testchip in single-chiplet arrangement
• authoring high-quality research papers for leading conferences and journals and presenting findings at international conferences.
• managing technical milestones for the project and providing technical guidance to PhD and master’s students within the group.

The appointment can commence immediately with a 1-year contract, with prospect of extension. Salary will be commensurate with qualifications and experience.

Qualifications

• a PhD degree in either Electrical Engineering or strictly related (e.g., Computer, Electronics, Communication, or Information Engineering).
• Knowledge on circuit architectures, transistor-level design.
• Knowledge on silicon chip design, EDA tools.
• Ability to work independently and collaboratively in a team environment.
• Good communication and interpersonal skills.
• open to fixed term contract.