Research Fellow (IC Designer)

NATIONAL UNIVERSITY OF SINGAPORE; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

National University of Singapore (NUS) invites applications for a Research Fellow in the SHINE Centre 2.0 within the Department of Electrical and Computer Engineering. The role focuses on physical, thermal and circuit-to-system modeling, and on developing predictive power management frameworks with test-chip demonstrations.

The successful candidate will author papers for leading conferences and journals, manage project milestones, and provide technical guidance to PhD and master’s students.

Qualifications

• A PhD degree in Electrical Engineering or strictly related field (e.g., Computer, Electronics, Communication, or Information Engineering).
• Knowledge on circuit architectures, transistor-level design.
• Knowledge on silicon chip design, EDA tools.
• Ability to work independently and collaboratively in a team environment.
• Good communication and interpersonal skills.
• Open to fixed term contract.

Responsibilities

• Model physical, thermal and circuit-to-system aspects; develop design exploration, architecture and validation/testing framework.
• Perform high-level exploration and modeling for predictive power management.
• Develop predictive power management from circuits to voltage-aware model optimization and test chip demonstration.
• Develop predictive power management from circuits to voltage and temperature-aware model optimization and test chip demonstration.
• Enable predictive power management runtime adaptation for accurate event detection with test chip demonstration.
• Integrate voltage/temperature-aware circuits, models and runtime adaptation for accurate event detection.
• Publish high-quality research papers and present findings at international conferences.
• Manage technical milestones and guide PhD and master's students within the group.

Skills

Independent work

Interpersonal skills

Communication

Education

PhD in Electrical Engineering or related field

Tools

EDA tools

Job description

Job Description

We are looking for a Research Fellow for the (SHINE) Centre 2.0 co-led by Professor Massimo Alioto, at the Department of Electrical and Computer Engineering, National University of Singapore (NUS).

• physical, thermal and circuit-to-system modeling, design exploration, architecture and validation/testing framework
• high-level exploration and modeling for predictive power management
• predictive power management from circuits to voltage-aware model optimization and test chip demonstration
• predictive power management from circuits to voltage and temperature-aware model optimization and test chip demonstration
• predictive power management runtime adaptation for accurate event detection with test chip demonstration
• full integration of voltage/temperature-aware circuits, models and runtime adaptation for accurate event detection
• authoring high-quality research papers for leading conferences and journals and presenting findings at international conferences.
• managing technical milestones for the project and providing technical guidance to PhD and master's students within the group.

The appointment can commence immediately with a 1-year contract, with prospect of extension. Salary will be commensurate with qualifications and experience.

Qualifications

• A PhD degree in either Electrical Engineering or strictly related (e.g., Computer, Electronics, Communication, or Information Engineering).
• Knowledge on circuit architectures, transistor-level design.
• Knowledge on silicon chip design, EDA tools.
• Ability to work independently and collaboratively in a team environment.
• Good communication and interpersonal skills.
• Open to fixed term contract.