IC Design Engineer

Avago Technologies Intl' Sales Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Avago Technologies Intl' Sales Pte Ltd in Singapore seeks an experienced R&D engineer to design and implement high-performance System-On-Chip ASICs. The role focuses on design and physical implementation, leading teams and collaborating with RTL and PD teams.

Requirements include 7+ years in Electrical/Electronics/Computer engineering, expertise with Cadence, Synopsys, Mentor, Ansys for P&R, Spice, DRC/LVS, STA and Power Integrity, plus scripting with Perl, Tcl, Python.

Qualifications

• Degree or higher in Electrical/Electronics/Computer engineering with 7+ years of relevant experience.
• Familiarity with VLSI design tools for Place & Route, spice simulation, DRC/LVS, STA and Power Integrity.
• Strong analytical and cross-functional collaboration skills.
• Experience with Perl, Tcl and Python scripting.

Responsibilities

• Collaborate with RTL and Physical Design teams to resolve timing violations.
• Use commercial and in-house EDA tools for large ASIC design in advanced nodes.
• Contribute to design flow and methodology development for deep submicron processes.

Skills

Team leadership

Analytical problem solving

Cross functional collaboration

Customer relationship management

Education

Electrical/Electronics/Computer engineering degree

Tools

Cadence

Synopsys

Mentor

Ansys

Job description

1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key competencies required are:

• Working experience leading team in physical design implementation of large ASICs (500 to 800 million gates complexity).
• Demonstrated ability in providing technical support to customers and managing customer working relationship.
• Demonstrated strong technical hands‑on competency in using leading edge physical design EDA tools in projects.
• In-depth CPU/DSP architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.
• Collaborating with RTL and Physical Design teams to resolve timing violations through design or constraint optimization.

2. Utilize commercial and in-house EDA tools for the design and implementation of 500 ~ 800 million gate integrated circuits in 5nm/3nm/2nm process technologies.

3. Opportunity to participate in innovation, design flow and methodology development to address challenges of designing into deep submicron processes and state-of-the-art ASIC design for computing and networking products

Qualifications: Requirements

1. Degree, Masters or PhD in Electrical/Electronics/Computer engineering with 7 years or more experience in a relevant field.

2. Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity

3. Strong analytical problem‑solving skills and the ability to collaborate in cross‑functional team environments

4. Experience in Perl, Tcl & Python Scripting languages