NAND Design Rule Engineer — Process Integration

Micron Memory Malaysia Sdn Bhd

Singapore

On-site

SGD 120,000 - 180,000

Full time

14 days+

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Job summary

Micron Memory Malaysia Sdn Bhd in Singapore is seeking an E5/MTS/SMTS NAND Design Rule Engineer to support the development and high-volume manufacturing of advanced 3D NAND technologies. You will lead design-rule and PDK deliverables, collaborating across process integration, devices, and layout teams to ensure quality, documentation, and timely execution in both R&D and production programs.

The candidate will possess a PhD or equivalent experience with strong CAD tool proficiency, semiconductor

Qualifications

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; or Master’s with 8+ years; or bachelor’s with 13+ years in the semiconductor industry (Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development).
Hands-on exposure to PDK, design rule, and layout; proficiency with CAD tools such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE.
Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge.
Demonstrated ability to resolve complex issues and communicate clearly under pressure.
Understanding of 3D NAND process flow and major NAND components (e.g., bit-line sensing, word-line driver, data path, and analog circuits).
Familiarity with CAD group interactions, data post-processing, and data transfer from design databases to reticles.
Preferred: prior experience in R&D for NAND or other memory technologies.

Responsibilities

Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for both R&D and production designs.
Own program execution and milestones from kickoff through end-of-life.
Partner with stakeholders across Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
Ensure high quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.
Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination.
Maintain strong, proactive communication with key stakeholders and escalate issues early with data-driven options.
Drive continuous improvement in design-rule pathfinding and document learnings that improve production parts still in design.