NAND Design Rule Lead — 3D NAND Innovation, Singapore

Micron Technology, Inc.; Singapore; On-site; SGD 150,000 - 230,000; Full time

Job summary

Micron Singapore seeks a Manager for NAND Design Rule/Process Integration to lead a team supporting the development and large-scale production of advanced 3D NAND technologies. This role focuses on accurate design-rule and PDK results, with rigorous documentation across R&D and manufacturing teams.

The ideal candidate will have a PhD or equivalent with extensive NAND experience, strong CAD/EDA skills, and a proven ability to deliver under pressure while coordinating across multiple functions and

Qualifications

• PhD or Master with extensive semiconductor R&D and NAND experience.
• Experience with PDK, design rules, and layout is required.

Responsibilities

• Lead the release of design rules and PDK deliverables; coordinate DRC waivers, mask definitions, and mask reviews for both R&D and production developments.
• Own program execution and achievements from kickoff through end-of-life.
• Partner with collaborators across Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
• Ensure high quality and documentation for Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Collaborate with Yield Improvement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.
• Build and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.
• Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination.
• Maintain strong, proactive communication with key collaborators and bring up issues early with data-driven options.
• Drive continuous improvement in design-rule pathfinding and document takeaways that improve production parts still under development.

Skills

Leadership in R&D NAND

Communication under pressure

Education

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science

Master’s degree / Bachelor’s degree with extensive semiconductor experience

Tools

Cadence Virtuoso

K2View

Mentor Graphics DRC/RVE

Job description

Micron Singapore seeks a Manager for NAND Design Rule/Process Integration to lead a team supporting the development and large-scale production of advanced 3D NAND technologies. This role focuses on accurate design-rule and PDK results, with rigorous documentation across R&D and manufacturing teams.

The ideal candidate will have a PhD or equivalent with extensive NAND experience, strong CAD/EDA skills, and a proven ability to deliver under pressure while coordinating across multiple functions and