NAND Design Rule Engineer — Process Integration

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD; Singapore; Vor Ort; SGD 180.000 - 240.000; Vollzeit

Zusammenfassung

Micron Technology, Inc. in Singapore is seeking an experienced E5/MTS/SMTS NAND Design Rule / Process Integration engineer to support development and high-volume manufacturing of advanced 3D NAND technologies.

You will drive design-rule and PDK deliverables and coordinate with process integration, devices, layout, modeling, and quality teams to ensure timely execution across R&D and production programs. You will own program milestones from kickoff to end-of-life, maintain high-quality DRCs, and

Qualifikationen

• PhD in Electrical Engineering, Microelectronics, Physics or Semiconductor Materials Science with 5+ years of relevant experience
• Hands-on exposure to PDK, design rules and layout (including minor layout work)
• Proficiency with CAD tools such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE (or equivalent) is a MUST
• Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge is a MUST
• Understanding of 3D NAND process flow and major NAND components (bit-line sensing, word-line driver, data path, and analog circuits)
• Familiarity with CAD group interactions, data post-processing, and data transfer from design databases to reticles
• Preferred: prior experience in R&D for NAND or other memory technologies

Aufgaben

• Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for both R&D and production designs
• Own program execution and milestones from kickoff through end-of-life
• Partner with stakeholders across Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas to guide new 3D NAND generations
• Ensure high quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviations and exceptions
• Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions
• Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels
• Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination
• Maintain strong, proactive communication with key stakeholders and elevate issues early with data-driven options
• Drive continuous improvement in design-rule pathfinding and document learnings that improve production parts still in design

Kenntnisse

PDK design rules

CAD tools proficiency

Semiconductor device physics

VLSI silicon processing

Problem solving under pressure

Cross-functional collaboration

Ausbildung

PhD in Electrical Engineering / Microelectronics / Physics / Semiconductor Materials Science

Master’s degree with 8+ years of experience

Bachelor’s degree with 13+ years of experience

Tools

Cadence Virtuoso

K2View

Mentor Graphics DRC/RVE

Jobbeschreibung

Micron Technology, Inc. in Singapore is seeking an experienced E5/MTS/SMTS NAND Design Rule / Process Integration engineer to support development and high-volume manufacturing of advanced 3D NAND technologies.

You will drive design-rule and PDK deliverables and coordinate with process integration, devices, layout, modeling, and quality teams to ensure timely execution across R&D and production programs. You will own program milestones from kickoff to end-of-life, maintain high-quality DRCs, and