Front-End ASIC Design & Verification Engineer (RTL/UVM)

DADACONSULTANTS PTE. LTD.

Singapore

On-site

SGD 60,000 - 90,000

Full time

14 days+

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Benefits offered by this job

Opportunity to work on advanced ASIC/SoC projects
Clear career progression in chip design and verification

Job summary

DADACONSULTANTS PTE. LTD. is seeking a front-end engineer in Singapore to work on high-performance chip systems. The role focuses on designing RTL modules and developing verification plans for ASIC/SoC projects. Candidates should have a strong foundation in digital design, familiarity with Verilog/SystemVerilog, and be enthusiastic about real-world applications in chip development.

The position offers clear career progression in a collaborative environment that emphasizes both design and verification.

Qualifications

  • Bachelor’s degree or above in Electrical Engineering, Computer Engineering, or related fields.
  • Understanding of digital design fundamentals and IC development flow.
  • Familiarity with Verilog/SystemVerilog and basic RTL design concepts.

Responsibilities

  • Design and implement RTL modules using Verilog/SystemVerilog for ASIC/SoC projects.
  • Develop and execute verification plans, including testbench development using UVM methodology.
  • Perform functional verification, debugging, and coverage analysis to ensure design correctness.

Skills

Verilog/SystemVerilog
UVM Methodology
Python
Scripting
Digital design fundamentals

Education

Bachelor’s degree in Electrical Engineering
Bachelor’s degree in Computer Engineering

Job description

DADACONSULTANTS PTE. LTD. is seeking a front-end engineer in Singapore to work on high-performance chip systems. The role focuses on designing RTL modules and developing verification plans for ASIC/SoC projects. Candidates should have a strong foundation in digital design, familiarity with Verilog/SystemVerilog, and be enthusiastic about real-world applications in chip development.

The position offers clear career progression in a collaborative environment that emphasizes both design and verification.

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