Lead Research Engineer — FOWLP & 2.5D Packaging

A*STAR RESEARCH ENTITIES

Singapore

On-site

SGD 120,000 - 180,000

Full time

14 days+

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Job summary

The Institute of Microelectronics (IME) in Singapore seeks a Lead Research Engineer to advance fan-out wafer level packaging (FOWLP) integration with fine pitch multi-layer RDL and micro bump interconnections for heterogeneous multi-chiplet integration on ultra large 2.5D interposers for AI applications.

Candidate should have 5–10 years in semiconductor fabrication process integration, including wafer-level bumping and RDL, with strong analytical and leadership abilities to mentor junior

Qualifications

Bachelors or Masters in a relevant engineering or science field.
Experience in wafer-level packaging or FOWLP preferred.

Responsibilities

Process integration development for high density multi-chip fan-out packaging.
Develop capabilities like fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene.
Establish FOWLP integration flows to meet partner requirements.
Plan loops and collaborate with process modules for materials evaluation.
Coordinate and support engineering builds using packaging processes.
Lead projects and mentor colleagues in semiconductor tech.

Skills

Analytical skills

Problem solving

Data analysis

Design of Experiments

Communication

Collaboration

Education

Bachelor/Master in Materials Science and Engineering / Mechanical / Chemical / Electronics / Electrical & Computer Engineering

Tools

Lithography

Plating

Etching

RDL

Bumping

Job description

Candidate should have 5–10 years in semiconductor fabrication process integration, including wafer-level bumping and RDL, with strong analytical and leadership abilities to mentor junior

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