Lead ASIC RTL/SoC Design Engineer for AI In-Memory

TETRAMEM INC; Singapore; On-site; SGD 80,000 - 180,000; Full time

Job summary

TetraMem is hiring a senior RTL/SoC engineer to drive RTL design, simulation, and verification for ASIC/SoC products. You will collaborate with backend teams, optimize PPA, and mentor junior engineers in a fast-paced startup environment.

The role requires strong Verilog/SystemVerilog expertise, experience with VCS/Verdi, and familiarity with AMBA protocols, ARM cores, and IP integration across complex SoC architectures.

Qualifications

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design.
• Experience with Verilog and SystemVerilog.
• Experience with pre-layout simulation and post-layout simulation.
• Understanding of the design flow and ability to work with the backend team.
• Familiarity with AMBA APB AXI Protocol and core architectures (e.g., ARM).
• Ability to create innovative architectures and lead engineering teams in a startup environment.

Responsibilities

• Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
• Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.
• Conduct Power, Performance, and Area (PPA) analyses to optimize design trade-offs.
• Collaborate with backend team during RTL coding, implementation, and synthesis to enable successful tapeout.
• Develop and maintain reusable IPs for AI and in-memory computing applications.
• Support Post-Si testing and validation to ensure product quality.
• Mentor junior engineers and contribute to design reviews and cross-functional discussions.
• Stay updated on RTL design trends to improve product quality and efficiency.

Skills

Verilog

SystemVerilog

UVM

Place-and-Route

STA

EM/IR/Power

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

VCS

Verdi

Job description

TetraMem is hiring a senior RTL/SoC engineer to drive RTL design, simulation, and verification for ASIC/SoC products. You will collaborate with backend teams, optimize PPA, and mentor junior engineers in a fast-paced startup environment.

The role requires strong Verilog/SystemVerilog expertise, experience with VCS/Verdi, and familiarity with AMBA protocols, ARM cores, and IP integration across complex SoC architectures.