Layout Engineer

SILITH TECHNOLOGY PTE. LTD.; Singapore; On-site; SGD 42,000 - 66,000; Full time

Job summary

SILITH TECHNOLOGY PTE. LTD. is seeking a layout engineer to transform design specifications into concrete chip layouts in Singapore.

The role involves advancing layout from lower modules to full-chip placement, routing, and verification, while collaborating closely with design engineers to meet layout requirements and plan floor layouts. The candidate should have a bachelor's degree in microelectronics or electronic engineering and at least 1 year in semiconductors, with proficiency in reading

Qualifications

• Bachelor's degree in microelectronics, electronic engineering, or related field.
• Minimum 1 year of semiconductor industry experience.
• Proficient in reading and understanding foundry process flow and design rule documents.
• Experience with tape-out processes is preferred.

Responsibilities

• Convert design specification documents into layout designs.
• Perform layout design from lower-level modules to top-level placement, routing, and verification.
• Communicate closely with design engineers to understand layout requirements and assist in layout floor planning/design.
• Develop layout design guidelines and checklists for layout inspection, verification, and design documentation archiving;
• Handle project tape-out activities
• Other ad-hoc tasks as assigned by supervisors

Skills

Layout design

Design rule comprehension

Foundry process flow

Education

Bachelor's degree in Microelectronics / Electronic Engineering

Tools

Python for layout design

Calibre DRC runsets

Job description

Responsibilities

• Convert design specification documents into layout designs
• Perform layout design from lower-level modules to top-level placement, routing, and verification
• Communicate closely with design engineers to fully understand layout requirements, assist in layout floor planning/design, and complete layout design for circuit modules and full-chip integration
• Develop layout design guidelines and checklists for layout inspection, verification, and design documentation archiving;
• Handle project tape-out activities
• Other ad-hoc tasks as assigned by supervisors

Requirements

• Bachelor's Degree in Microelectronics, Electronic Engineering, or related fields;
• Minimum 1 year of experience in semiconductor industry
• Proficient in reading and understanding Foundry process flow and design rule documents, fully understand the device structures of the process technology used, and establish standard cell libraries;
• Experience with Python for layout design
• Experience in writing Calibre DRC runset scripts
• Experience or knowledge with the Tape-Out process are preferred.