Analog Mixed-Signal Layout Intern

Astera Labs; Singapore; On-site; SGD 13,000 - 26,000; Full time

Job summary

Astera Labs seeks a motivated Analog Mixed-Signal Layout Intern to assist in the design and layout of high-performance analog and mixed-signal IP blocks. You will work with experienced engineers to translate schematic designs into silicon, gaining hands-on experience with advanced technology nodes and CAD tools.

Responsibilities include LVS, DRC, PEX checks, floor planning, placement, routing, and matching for analog blocks, while collaborating to optimize performance and reliability.

Qualifications

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of analog/mixed-signal IC design concepts.
• Familiarity with EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics.
• Basic understanding of matching techniques, layout symmetry, and common centroid structures.
• Eagerness to learn advanced layout methodologies for high-speed and low-noise analog design.

Responsibilities

• Assist in layout design of analog and mixed-signal circuits such as: Current mirrors, differential pairs, op-amps, bandgaps, comparators.

Skills

Analytical skills

Problem solving

Analog/mixed-signal basics

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Cadence Virtuoso

Synopsys

Mentor Graphics

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

We are seeking a motivated Analog Mixed-Signal Layout Intern to assist in the design and layout of high-performance analog and mixed-signal IP blocks. You will work closely with experienced layout and circuit design engineers to translate schematic designs into silicon, gaining hands‑on experience with advanced technology nodes and CAD tools.

Key Responsibilities

• Assist in layout design of analog and mixed‑signal circuits such as: Current mirrors, differential pairs, op‑amps, bandgaps, comparators…
• Perform layout‑vs‑schematic (LVS), design‑rule checks (DRC), and parasitic extraction (PEX) to ensure design quality and manufacturability
• Support floor planning, placement, routing, and matching for analog blocks following layout best practices (symmetry, shielding, guard rings, etc.)
• Work with circuit designers to optimize layout for performance, area, and reliability (minimize mismatch, noise coupling, IR drop).
• Document layout work and contribute to layout review checklists and verification reports.

Qualifications

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of analog/mixed‑signal IC design concepts.
• Familiarity with EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics.
• Basic understanding of matching techniques, layout symmetry, and common centroid structures. Strong analytical and problem‑solving skills.
• Eagerness to learn advanced layout methodologies for high‑speed and low‑noise analog design.

What You’ll Gain

• Exposure to industry‑standard AMS design flows and tools.
• Opportunity to study high speed layout techniques.
• Mentorship from experienced Circuit and AM layout engineers.
• Hands‑on experience with real design projects leading to tape‑out.

Preferred Skills (Nice To Have)

• Experience with version control systems (e.g., Git, Perforce).
• Knowledge of CMOS, FINFET devices structure.
• Familiarity with analog layout techniques and parasitic extraction.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.