Junior/Senior IP DK design Engineer (Semiconductor)

talent trader group pte. ltd.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

talent trader group pte. ltd. is seeking an experienced IC design engineer to own library characterization for Memory IP and related products, driving automation improvements in characterization flow.

Responsibilities include generating Design Kits (DK) with Liberty (.lib), CDL, IBIS, Verilog, LEF and performing pre-QA verification to ensure functional correctness and tool compatibility across EDA flows. A 3+ year background in IC design or DK generation is required.

Qualifications

• Bachelor's or Master's in Microelectronics or related field.
• At least 3 years of hands-on IC design, IP development, or DK generation.
• Strong understanding of Liberty format and syntax, timing, constraint, and power modeling concepts.
• Familiarity with timing, power, and noise models such as NLDM, CCS, LVF, and OCV.
• Knowledge of library characterization methodologies, with proficiency in characterization tools such as Liberate, Liberate MX, or SiliconSmart.
• Solid understanding of SPICE simulation and the ability to develop, debug, and validate SPICE testbenches.
• Familiarity with the ASIC design flow and experience using EDA tools for synthesis, STA, P&R, and power analysis.
• Proficient in scripting and automation using Perl, Python, Tcl, and Skill.

Responsibilities

• Take ownership of library characterization activities for Memory IP and other IP products, while driving improvements in characterization flow automation.
• Generate and maintain Design Kits (DK) for Memory IP and other IPs, including deliverables such as Liberty (.lib), CDL, IBIS, Verilog, LEF, and related files.
• Conduct pre-QA verification for Memory IP to ensure functional correctness, performance accuracy, and compatibility across a range of EDA tools.

Skills

Liberty format knowledge

SPICE testbench development

ASIC/DK development

Problem solving

Education

Bachelor's or Master's in Microelectronics

Tools

Liberate

Liberate MX

SiliconSmart

Job description

Responsibilities

• Take ownership of library characterization activities for Memory IP and other IP products, while driving improvements in characterization flow automation.
• Generate and maintain Design Kits (DK) for Memory IP and other IPs, including deliverables such as Liberty (.lib), CDL, IBIS, Verilog, LEF, and related files.
• Conduct pre-QA verification for Memory IP to ensure functional correctness, performance accuracy, and compatibility across a range of EDA tools.

Requirements

• Bachelor's or Master's degree in Microelectronics or a related field
• At least 3 years of hands-on experience in IC design, IP development, or Design Kit (DK) generation.
• Strong understanding of Liberty format and syntax, including timing, constraint, and power modeling concepts. Familiarity with timing, power, and noise models such as NLDM, CCS, LVF, and OCV is required.
• Knowledge of library characterization methodologies, with proficiency in characterization tools such as Liberate, Liberate MX, or SiliconSmart.
• Solid understanding of SPICE simulation and the ability to independently develop, debug, and validate SPICE testbenches.
• Familiarity with the ASIC design flow and experience using EDA tools for synthesis, static timing analysis (STA), place-and-route (P&R), and power analysis.
• Proficient in scripting and automation using languages such as Perl, Python, Tcl, and Skill.