Intern - PEE DIFFUSION

1100 Micron SemiAsiaOP Pte Ltd; Singapore; On-site; SGD 33,480 - 55,800; Full time

Job summary

1100 Micron SemiAsiaOP Pte Ltd is seeking an intern in Singapore to drive yield improvement initiatives through advanced analytical techniques. The intern will focus on CMOS matching analysis and Wafer Edge Exclusion programs, aiming to enhance manufacturing performance by identifying key yield losses.

The role requires a strong background in semiconductor processes and data analytics, as well as problem-solving skills to address complex engineering challenges effectively.

Qualifications

• Strong background in semiconductor process engineering, yield analysis, and defectivity characterization.
• Proficiency in data analytics, statistical analysis, and the use of inspection and inline metrology tools.
• Demonstrated ability to perform root-cause analysis and translate data insights into manufacturing improvements.

Responsibilities

• Drive yield improvement initiatives through CMOS matching analysis.
• Conduct offload interaction studies to diagnose yield differences.
• Analyze data to establish root-cause relationships between variation and yield.

Skills

Semiconductor process engineering

Data analytics

Statistical analysis

Root-cause analysis

Problem-solving

Education

Background in semiconductor engineering or related field

Tools

Metrology tools

Data analysis software

Job description

F10N/W CMOS Matching and RegE Wafer Edge Exclusion (WEE) Program

The intern will be responsible for driving yield improvement initiatives through CMOS matching analysis and RegE Wafer Edge Exclusion (WEE) program. The role focuses on identifying inline mismatches, reducing wafer edge‑related yield loss, and developing robust analytical solutions to enable sustainable manufacturing performance.

Key Responsibilities

• Conduct fab‑to‑fab offload interaction studies to identify and diagnose inline mismatches between N and W processes that contribute to yield differences.
• Perform detailed bevel characterization to assess defectivity performance differences and quantify their impact on inline die loss.
• Analyze cross‑module data to establish root‑cause relationships between process variation and yield performance.
• Drive key WEE performance metrics, including 22UE capability and 1H edge coat performance, to maximize overall yield.
• Identify, troubleshoot, and mitigate process detractors impacting WEE metrics and edge‑related yield loss.
• Develop and implement an accurate Wafer Inspection System (WIS) algorithm to reliably capture true 22UE performance while excluding known detractors such as wet moisture signature.

Project Scope

Apply advanced analytical and data‑mining tools to extract actionable insights and identify yield improvement opportunities. Integrate inline, defect, and inspection data to support root‑cause analysis and data‑driven decision making. Exercise strong engineering judgment to prioritize actions, balance risk, and drive effective technical solutions across cross‑functional teams.

Key Deliverables

• Close the F10 N/W yield mismatch gap of approximately 0.9%.
• Drive the RegE WEE program toward a 160s edge exclusion target of zero non‑live dies.
• Deliver a robust WIS algorithm that excludes wet moisture signatures while accurately reflecting true 22UE performance.

Required Skills and Competencies

• Strong background in semiconductor process engineering, yield analysis, and defectivity characterization.
• Proficiency in data analytics, statistical analysis, and use of inspection and inline metrology tools.
• Demonstrated ability to perform root‑cause analysis and translate data insights into manufacturing improvements.
• Strong ownership mindset, problem‑solving skills, and ability to collaborate effectively across modules and functions.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.