Principal Engineer (Integration Yield Defect)

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) in Singapore is looking for experienced individuals to supervise Associate Engineers and wafer tech operators, ensuring smooth 24/7 inline operations.

The successful candidate will have a strong background in electrical or microelectronics engineering, coupled with significant experience in defect analysis and yield enhancement. The position requires effective leadership and communication skills, with a focus on continuous improvement.

Qualifications

• 5-8 years of relevant work experience in high volume manufacturing of electronics components in MNC or semi-conductor industry.
• Familiar with defect analysis and yield enhancement in wafer process.
• Strong analytical skills and able to work under pressure in a fast pace environment.

Responsibilities

• Supervise YDD Associate Engineers and wafer tech operators.
• Train and certify DO Associate Engineers on recipe creation.
• Perform defect characterization by process tools.
• Automate daily activities to improve troubleshooting speed.

Skills

Defect analysis

Yield enhancement

Leadership skills

Analytical skills

Communication skills

Education

Masters or Bachelor Degree in Electrical / Electronics / Chemical / Microelectronics Engineering

Tools

MS Power Point

Excel

Excel VBA

Job description

Job Description

• Supervise YDD Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation
• Train and certify DO Associate Engineers on recipe creation and defect source knowledge
• Maintain and enhance internal SOP/CAS and involve in internal;/external audit
• Operate FIB/SEM/EDX for inline failure analysis
• Operate and create recipes in Brightfield, Darkfield and other YDD tools
• Maintain and housekeep Brightfield, Darkfield and recipes of other YDD tools
• Perform partition analysis on defect source and detailed reports on issues
• Build and develop defect source library and tool’s defect source fingerprinting
• Track inline defect performance by layer/process tool/chamber on weekly basis
• Perform killer ration analysis
• Perform defect characterization by process tools
• Continuous improvement activities on defect reductions with Modules / vendors / equipment team
• Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities
• Provide scan support in low yield investigation & co-work with PI/YE/PE on technology & device specific yield enhancement activities
• Automate daily activities to improve troubleshooting speed of team
• Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems

Job Requirements

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Microelectronics Engineering
• 5-8 years of relevant work experience in high volume manufacturing of electronics components in an MNC or semi-conductor industry preferred
• Familiar and experience in defect analysis and yield enhancement in wafer process.
• Excellent interpersonal and communication skills with good leadership capability
• Strong analytical skills and able to work under pressure in a fast pace environment
• Proficient with MS Power Point, Excel, Excel VBA, [e-mail]