Integrated Circuit Designer - Layout

Astera Labs; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Astera Labs is seeking a highly motivated Integrated Circuit Designer to work with layout and design engineers across multiple time zones. The role focuses on designing and developing complex CMOS IC layouts for advanced nodes, with emphasis on floor planning, parasitic minimization, and adherence to EMIR/antenna DRC rules.

The candidate will also assist in process technology advice, equipment maintenance, and development of test programs to verify performance, requiring a bachelor’s degree in

Qualifications

• Bachelor’s degree in electrical engineering.
• 2+ years of experience in layouts for high-speed analog ICs in finFET technology.
• Experience with layout extraction tools and layout parasitic analysis.
• EMIR rules and antenna DRC aware layout practices.
• Experience writing SKILL and TCL scripts is highly recommended.

Responsibilities

• Design and develop the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams, including floor planning and building block layouts for PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes.
• Manage manufacturing process of the products, including technology yield and performance.
• Develop test programmes and procedures to ensure the products meet performance specifications.
• Provide advice on semiconductor process technology and maintain/repair semiconductor process equipment.

Skills

High-speed analog layout

SKILL scripting

TCL scripting

Parasitic analysis

EMIR rules

Antenna DRC

Education

Bachelor's degree in Electrical Engineering

Tools

Layout extraction tools

Job description

The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones

As an Integrated Circuit Designer, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Key Job Duties:

• The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]
• The management of manufacturing process of the products, including technology yield and performance of the products.
• The development of test programmes and procedures to ensure the products meet their performance specifications.
• The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications:

• At least a bachelor’s degree in electrical engineering

Required Experience:

• 2+ years of experience in the development of layouts for highspeed analog IC designs in finFET technology.
• Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
• EMIR and antenna DRC rules aware layout practices.
• Experience writing SKILL and TCL scripts is highly recommended