IC Synthesis & STA Engineer — Timing & Low-Power

PICOHEART (SG) PTE. LTD.; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

ByteDance seeks an experienced IC Design Engineer to drive the silicon design flow from RTL to GDSII, focusing on synthesis, SDC constraints, and power optimization for advanced chip projects. The role collaborates with frontend and backend teams to ensure tight timing and robust DFT integration.

The candidate brings 3+ years in IC design, strong Verilog/SystemVerilog and EDA tool proficiency, and a track record in low‑power implementation and timing closure.

Qualifications

• Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.
• 3+ years of experience in IC design with a focus on sdc, synthesis, timing signoff, low‑power implementation, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to‑GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, PrimeTime/Tempus, Formality, Conformal LP).

Responsibilities

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constrains (SDC) preparation and tuning, and conduct hierarchical/full‑chip STA signoff and timing closure.
• Implement low‑power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front‑end engineers for architectural exploration and planning.
• Work with backend engineers on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Skills

Verilog/SystemVerilog

Synthesis

Timing signoff

Low-power design

Power optimization

SDC

RTL-to-GDSII flow

EDA tools

Fusion Compiler

Genus/Innovus

PrimeTime/Tempus

Formality

Conformal LP

Education

Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field

Tools

Fusion Compiler

Genus/Innovus

PrimeTime/Tempus

Formality

Conformal LP

Job description

ByteDance seeks an experienced IC Design Engineer to drive the silicon design flow from RTL to GDSII, focusing on synthesis, SDC constraints, and power optimization for advanced chip projects. The role collaborates with frontend and backend teams to ensure tight timing and robust DFT integration.

The candidate brings 3+ years in IC design, strong Verilog/SystemVerilog and EDA tool proficiency, and a track record in low‑power implementation and timing closure.