IC Design Layout Engineer

NUVOTON TECHNOLOGY SINGAPORE PTE. LTD.; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

NUVOTON TECHNOLOGY SINGAPORE PTE. LTD. is seeking a skilled IC layout engineer to develop physical layouts for CMOS/BiCDMOS analog ICs used in SerDes, automotive, and battery management systems.

You will collaborate with design teams across regions to ensure robust layouts meeting stringent performance and reliability targets. The role requires knowledge of layout techniques, DRC/LVS compliance, and familiarity with 28nm/22nm CMOS and FinFET processes, along with strong problem-solving and

Qualifications

• Bachelor’s degree or diploma with relevant IC layout experience.
• Good knowledge of IC layout design, verification and DRC/LVS.
• Proficiency with industry tools such as Cadence Virtuoso, Synopsys IC Compiler and Mentor Calibre.
• Strong understanding of CMOS design, manufacturing processes and DFM techniques.
• Strong problem-solving, attention to detail and teamwork.
• Experience with 28nm, 22nm planar CMOS and FinFET tech is a plus.
• 2–5 years of analog IC layout experience; fresh graduates also welcome.

Responsibilities

• Design high-quality block and top block-level IC layouts for analog, mixed-signal, and high-speed interface circuits.
• Ensure designs comply with foundry rules like DRC/LVS and support post-layout extraction and debugging.
• Apply layout techniques to meet matching, signal integrity, reliability, and post-layout performance.
• Apply best practices for 28nm, 22nm planar CMOS and FinFET technologies, including device placement and routing constraints.
• Collaborate with circuit designers and layout designers to optimize layout performance.
• Contribute to layout methodology improvements, automation scripts and documentation.
• Prepare and maintain accurate documentation of layout output, verification results, and explain them during design reviews.

Skills

IC Layout

DRC/LVS

Analog/Mixed-signal

Teamwork

Communication

Problem Solving

Education

Bachelor’s Degree in Electronics/Electrical Engineering

Diploma with relevant experience

Tools

Cadence Virtuoso

Synopsys IC Compiler

Mentor Calibre

Job description

You will be responsible for developing the physical layout of CMOS/BiCDMOS Integrated Circuit designs used in high-performance, high-speed analog ICs for SerDes applications, as well as for Automotive and Industrial Battery Management Systems. These products will enable the next generation of data communication systems using high-speed wireline transmission and empower the electrification of vehicles to achieve carbon neutrality. You will work closely with circuit design engineers both locally and overseas to deliver robust, high-quality layouts that meet stringent performance, signal integrity and reliability requirements.

Key responsiblities:

• Design high-quality block and top block-level IC layouts for analog, mixed-signal, and high-speed interface circuits


• Ensure that designs comply with foundry-specific rule like the DRC and LVS and support post-layout extraction and debugging


• Apply good layout techniques to meet matching, signal integrity, reliability requirements and good post layout performance


• Apply the best practices for 28nm, 22nm planar CMOS and FinFET technologies, including device placement, routing constraints and process-specific rules


• Collaborate closely with circuit designers and layout designers to optimize layout performance


• Contribute to layout methodology improvements, automation scripts and documentation


• Prepare and maintain accurate documentation of layout output, verification result judgement and explain them during design review

Requirements:

• Bachelor’s Degree in Electronics/ Electrical Engineering or Diploma with relevant experience


• Good knowledge in IC layout design, verification and design rule checking


• Proficiency in IC design software, such as Cadence Virtuoso, Synopsys IC Compiler and Mentor Graphics Calibre


• Strong understanding of CMOS design principles, semiconductor manufacturing processes and design-for-manufacturability techniques


• Good problem-solving skills, attention to detail and capability to work effectively in a team environment with good communication skills


• Experience with 28nm, 22nm planar CMOS and FinFET technologies will be a plus


• 2-5 years of analog IC layout design experience will be a plus. Fresh graduates from semiconductor(IC) design related course are also welcome to apply.