Layout Engineer, Analog ICs (CMOS/FinFET)

NUVOTON TECHNOLOGY SINGAPORE PTE. LTD.; Singapore; On-site; SGD 67,000 - 100,000; Full time

Job summary

NUVOTON TECHNOLOGY SINGAPORE PTE. LTD. is seeking a skilled IC layout designer to develop robust analog, mixed-signal, and high-speed interface layouts for SerDes, automotive, and battery management applications.

You will ensure compliance with foundry rules, perform post-layout checks, and collaborate with global design teams to optimize layout performance and reliability using 28nm/22nm CMOS and FinFET processes.

Qualifications

• Proficient in IC layout design, verification and DRC/LVS.
• Strong CMOS design understanding and manufacturability knowledge.
• Good communication and teamwork skills.
• Fresh graduates welcome with semiconductor coursework and potential.

Responsibilities

• Design high-quality block and top block-level IC layouts for analog, mixed-signal, and high-speed interface circuits.
• Ensure designs comply with DRC/LVS and support post-layout extraction and debugging.
• Apply layout techniques to meet matching, signal integrity and reliability requirements.
• Use 28nm/22nm CMOS and FinFET guidelines, including placement and routing constraints.
• Collaborate with circuit and layout designers to optimize performance and reliability.
• Contribute to layout methodology improvements, automation scripts and documentation.
• Prepare and maintain layout output and verification documentation for design reviews.

Skills

IC layout design

Problem solving

Teamwork

Communication

Education

Bachelor’s degree in Electronics/Electrical Engineering

Diploma with relevant experience

Tools

Cadence Virtuoso

Synopsys IC Compiler

Mentor Graphics Calibre

Job description

NUVOTON TECHNOLOGY SINGAPORE PTE. LTD. is seeking a skilled IC layout designer to develop robust analog, mixed-signal, and high-speed interface layouts for SerDes, automotive, and battery management applications.

You will ensure compliance with foundry rules, perform post-layout checks, and collaborate with global design teams to optimize layout performance and reliability using 28nm/22nm CMOS and FinFET processes.