HW System / SoC Architect

Search staffing services pte ltd; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Unknown company is seeking a senior SoC Architect to own the architecture of peripheral subsystems for wearable and IoT devices, balancing power budgets on sub-threshold silicon. The role is hands-on and interfaces with RTL, physical design, software, and field teams in Singapore.

You will define power/performance trade-offs, guide IP selection, and ensure robust integration from transistor to cable. A track record in SoC/ASIC architectures and strong communication are essential.

Qualifications

• Author architecture specifications for SoCs/ASICs or silicon IP implemented in RTL.
• 8+ years in SoC/ASIC architecture and design, or silicon IP development for wearables/IoT/mobile-class products.
• Hands-on experience architecting external interfaces: audio (I2S, PDM), imaging/display (MIPI CSI/DSI), USB/SPI/I2C.

Responsibilities

• Define power and performance models for full system dataflows across die, package, board, and software.
• Provide integration specifications for system interfaces and external power management.
• Support post-silicon validation and delivery of SoC functionality into mass production.
• Collaborate with RTL design, physical design, software, and marketing teams to align architectures.

Skills

SoC architecture

ASIC design

Hardware RTL

Systems thinking

Communication

Education

BSE/CS degree

Tools

RTL design tools

Job description

HW System / SoC Architect

Role Summary

We're looking for a senior SoC Architect to be the primary architectural voice for our Singapore engineering team. You'll own the architecture of our SoC's peripheral subsystems - audio, imaging and display, and high- and low-speed interfaces - designed for the extreme power budgets of battery-powered wearables and IoT devices.

On our sub-threshold silicon, external interfaces are often the single biggest driver of system power. That makes decisions most teams treat as routine - when a link wakes, what stays retained, how data moves without waking the CPU - first-order architectural problems. This role sits at the center of that challenge, spanning everything from the transistor to the cable in your hand.

This is a hands-on, individual-contributor role.

Responsibilities:

• Architecture specifications for the SoC’s peripheral subsystems: micro-architecture definition, flow and sequence diagrams, power and performance models, and pseudocode - the documents RTL design and verification teams implement
• Off-die interface definition - modes, electrical and protocol behavior, and integration requirements that account for boards, cables, connectors, PHYs, and the software driver model
• Debug at RTL and gate level with the design team when implementation raises questions the specification must answer
• Partnership with physical design to ensure robust, optimal implementation of what you specify
• Power and performance trade-off analysis across full system dataflows - die, package, board, and software - guiding both hardware and software development
• IP investigation, assessment, and selection - build-vs-license recommendations with the analysis to back them
• Integration specifications covering system interfaces and external power management
• Post-silicon analysis and support for delivery of SoC functionality into mass production
• Use case and test case definition in support of validation

Who you’ll work with

RTL design and verification, physical design, our FPGA bring-up team, software architecture, and colleagues in Marketing, Advanced Development, and our HQ architecture team plus customers and field teams on key features and competitive positioning.

Requirements:

• A track record of authoring architecture specifications for SoCs, ASICs, or silicon IP that hardware teams implemented in RTL - this is the core of the role
• 8+ years in SoC/ASIC architecture and design, or silicon IP development, for wearable, IoT, or mobile-class products (hardware/RTL background - not firmware or driver development)
• Hands-on experience architecting external interfaces: audio (I2S, PDM), imaging/display (MIPI CSI/DSI), and high/low-speed links (USB, SPI, I2C)
• Working knowledge of each interface on both sides of the package: board-level electrical constraints, cable/connector requirements (e.g., USB power delivery), PHY integration, and OS driver models
• Experience shipping low-power silicon architectures to market, from concept through post-silicon validation
• Strong systems-level thinking across the hardware/software boundary
• The ability to build consensus and drive alignment across distributed teams
• Excellent written and verbal communication
• BS in Electrical Engineering, Computer Engineering, or Computer Science

Nice to Have

• MS or PhD in a related field
• Experience with SoC fabric/interconnect, power management architecture, or UPF/power-aware design flows
• Hands-on work on advanced process nodes
• Familiarity with low-power mobile consumer systems, embedded imaging, or neural network processing

EA Personnel Registration No: R1106329

EA License No: 12C6254