Full-Chip Performance Modeling Engineer

Bitdeer Technologies Group; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive compensation

Career growth

Flexible work environment

Job summary

Bitdeer Technologies Group in Singapore is seeking a senior performance modeling engineer to lead full-chip models of the EtHash tile array, the NoC, and the 3D-DRAM bandwidth path. You will drive architecture decisions and partner with hash core, memory and compiler teams.

You will build cycle-approximate models in C++/SystemC and Python, perform roofline analyses, model traffic and QoS, and translate results into actionable recommendations for architecture freeze.

Qualifications

• 5+ years of performance modeling/architecture for SoCs or accelerators.
• Strong C++ and Python; SystemC or similar modeling framework.
• Solid understanding of memory hierarchy and NoC behavior.
• Experience turning models into architectural decisions.
• Team-oriented, able to collaborate across architecture, design and software.

Responsibilities

• Full-chip performance models in C++/SystemC and Python.
• Produce roofline analyses mapping workloads to memory hierarchy.
• Model NoC contention, memory bandwidth and QoS under realistic traffic.
• Run parameter sweeps and provide actionable recommendations.
• Correlate model predictions with RTL, emulation, or silicon.
• Provide performance references and golden-model hooks.
• Maintain dashboards and trade-off decks for leadership.

Skills

C++

Python

SystemC

Architecture fundamentals

Performance modeling

Education

BS in Computer Science or Electrical Engineering

Tools

RTL emulation

Job description

Bitdeer Technologies Group in Singapore is seeking a senior performance modeling engineer to lead full-chip models of the EtHash tile array, the NoC, and the 3D-DRAM bandwidth path. You will drive architecture decisions and partner with hash core, memory and compiler teams.

You will build cycle-approximate models in C++/SystemC and Python, perform roofline analyses, model traffic and QoS, and translate results into actionable recommendations for architecture freeze.