Full-Chip Performance Modeling Architect

Bitdeer (NASDAQ: BTDR); Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud, headquartered in Singapore. We are seeking a performance modeling expert to build full-chip models that drive architecture decisions for our advanced NoC, tile array, and memory subsystem.

You will collaborate across hash core, memory and compiler groups, delivering cycle-approximate models, analyses, and clear recommendations that hit power and thermal targets while shaping the next generation of silicon.

Qualifications

• 5+ years in performance modeling and architecture for SoCs and accelerators.
• Strong C++ and Python; SystemC or similar modeling framework experience.
• Solid understanding of memory hierarchy, bandwidth, and NoC behavior.
• Ability to turn modeling results into architecture decisions, not just numbers.
• Comfortable collaborating across architecture, design and software teams.

Responsibilities

• Build and maintain full-chip cycle-approximate models of tile array, NoC and memory.
• Perform roofline analyses to map workloads to memory hierarchy.
• Model NoC contention and memory bandwidth under realistic traffic.
• Run architecture sweeps and translate results into actionable recommendations.
• Correlate models against RTL, emulation or silicon; document gaps and plan.
• Maintain dashboards and trade-off decks for leadership visibility.
• Provide golden-reference hooks for performance and verification teams.

Skills

Performance modeling

C++

Python

SystemC

Architecture knowledge

Job description

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud, headquartered in Singapore. We are seeking a performance modeling expert to build full-chip models that drive architecture decisions for our advanced NoC, tile array, and memory subsystem.

You will collaborate across hash core, memory and compiler groups, delivering cycle-approximate models, analyses, and clear recommendations that hit power and thermal targets while shaping the next generation of silicon.