Staff SoC Verification Engineer (FPGA/ASIC)

AMD

Singapore

On-site

SGD 90,000 - 150,000

Full time

14 days+
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Job summary

AMD is seeking a dedicated SoC verification professional to plan, develop, and execute verification of ASIC and FPGA designs. You will collaborate with distributed teams to ensure bug-free final designs and drive verification infrastructure.

A strong background in SystemVerilog, UVM, and scripting is essential. Singapore-based role requiring collaboration across sites, with a focus on testplan development, testbench creation, and regression management.

Qualifications

  • Bachelor’s or Master’s degree required in Computer Engineering, Electrical Engineering, or related field.
  • Hands-on experience with SystemVerilog, UVM, and verification methodologies.
  • Strong programming skills in C/C++ and scripting (Python/Perl).

Responsibilities

  • Verify next-generation ASIC and FPGA SoCs in a distributed team across sites/time zones.
  • Collaborate with design, software, and architecture teams to verify SoC designs.
  • Develop SoC testplans, testbenches, and testcases with functional coverage goals.
  • Manage regression testing and contribute to verification infrastructure improvements.
  • Develop both directed and random verification tests.
  • Debug failures and work with RTL/firmware engineers to fix defects.
  • Review coverage metrics and adjust tests to meet coverage targets.

Skills

Verilog/SystemVerilog
C/C++
Python/Perl
UVM

Education

Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering

Tools

UVM framework
Testbenches

Job description

AMD is seeking a dedicated SoC verification professional to plan, develop, and execute verification of ASIC and FPGA designs. You will collaborate with distributed teams to ensure bug-free final designs and drive verification infrastructure.

A strong background in SystemVerilog, UVM, and scripting is essential. Singapore-based role requiring collaboration across sites, with a focus on testplan development, testbench creation, and regression management.

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