Ultra-Low-Power Memory Design Engineer

Ambiq Micro, Inc.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Ambiq Micro, Inc. is seeking an experienced Memory Design Engineer to architect and validate embedded SRAM and RF IPs for ultra‑low‑power SoCs.

You will drive compiler architectures, memory peripheral optimization, and silicon correlation across conventional and near/ sub‑threshold voltages. The role requires strong Python scripting, Cadence tool fluency, and cross‑functional collaboration with architecture, physical design, and foundry teams.

Qualifications

• Experience developing embedded SRAM or Register File IP for advanced 12nm FINFET technologies and below.
• Proven ability to develop SRAM compiler architectures and configurable memory generation.
• Strong memory characterization and production‑quality Liberty (.lib) generation.
• Deep knowledge of low‑voltage SRAM operation, timing and power characterization.
• Scripting skills in Python, Tcl, or Perl, and cross‑functional collaboration.

Responsibilities

• Design ultra‑low power embedded SRAM and RF IPs for advanced SoCs.
• Develop SRAM compiler architectures with configurable memory options.
• Design and optimize memory peripherals (sense amps, drivers, decoders, etc.).
• Correlate simulation with silicon measurements; optimize for area and power.
• Analyze low‑voltage failure mechanisms and margins across voltage ranges.
• Drive memory yield through silicon debug, characterization and design tweaks.
• Develop automation scripts to improve compiler generation and testing efficiency.
• Collaborate with memory architecture, physical design, timing, DFT, and foundry teams.
• Support memory IP integration from architecture to production release.
• Document methodologies, results, and learnings from silicon.

Skills

SRAM architecture

Compiler design

Memory IP design

Memory characterization

Liberty model generation

Python scripting

Low-voltage memory operation

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering or related

Tools

Cadence Virtuoso

Spectre

HSPICE

Cadence Liberate MX

Monte Carlo simulations

Job description

Ambiq Micro, Inc. is seeking an experienced Memory Design Engineer to architect and validate embedded SRAM and RF IPs for ultra‑low‑power SoCs.

You will drive compiler architectures, memory peripheral optimization, and silicon correlation across conventional and near/ sub‑threshold voltages. The role requires strong Python scripting, Cadence tool fluency, and cross‑functional collaboration with architecture, physical design, and foundry teams.