Foundation IP Design Engineer

Avago Technologies Intl' Sales Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Avago Technologies Intl' Sales Pte Ltd in Singapore seeks energetic design engineers to join the Central Engineering Group. You will work on the development of foundation IP for AI products including memory compilers, logic cells, and custom macros across process tech.

Multiple experience levels are welcome. Responsibilities include architectural analysis, block design at transistor level, timing/power characterization, layout integration, and automation scripting.

Qualifications

• BS in Electrical or Computer Engineering required.
• 8+ years of related experience.
• Strong grounding in device physics and memory design.

Responsibilities

• Analyze memory architectures and tradeoffs.
• Design memory blocks at gate/transistor level.
• Simulate circuit designs with transistor-level simulators.
• Extract layout and perform post-layout verification.
• Floorplan physical implementation and layout integration.
• Integrate characterization flow for timing and power.
• Develop scripts to automate characterization, simulations and verification.
• Specify and verify memory behavioral and physical models.
• Document design specs, behavior, and timing diagrams.
• Help specify silicon test plans and correlate silicon to simulation data.

Skills

Memory compilers

Custom macros

Transistor level

Memory models

DFT & integration

Automation scripting

Communication/leadership

Multi-tasking

Education

BS in Electrical or Computer Engineering

Tools

Transistor level simulators

DFT tools

Job description

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Analyze different memory architectures and highlight the tradeoffs
• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyze the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and layout integration of design components
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioral and physical memory models
• Document the design specifications, behavioral description, and timing diagrams
• Help specify silicon test plan and correlate silicon to simulation data

Skillset Required

• Strong Expertise in development of memory compilers and custom macros of all types
• Deep understanding of transistor level circuit behavior and device physics
• Deep understanding of memory bitcell R/W margins and associated assist techniques
• Deep understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Good understanding of memory behavioral and physical models
• Good understanding of DFT schemes and chip level integration
• Proficient in running simulators, writing automation scripts, and are tools savvy
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking

Qualifications

Requires a BS in Electrical or Computer Engineering and 8 years of related experience