ASIC IC Physical Design Engineer - Tapeout & Timing

FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED SINGAPORE BRANCH; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED SINGAPORE BRANCH is seeking an experienced IC Physical Design Engineer to contribute to full-chip physical design development for FTDI products. You will work on tech file libraries, floor-planning, CTS, place and route, RC extraction and collaborate with front-end designers to meet timing closure.

The role requires a degree in Electrical/Electronic Engineering and 3+ years in ASIC flow layout design, with hands-on Verilog/VHDL experience and

Qualifications

• Degree or Master in Electrical/Electronic Engineering required.
• 3+ years in ASIC flow layout design with full-chip responsibilities.
• Experience from design to tape-out essential; timing closure experience preferred.

Responsibilities

• Full-chip IC physical design development for FTDI products.
• Tech file library preparation, floor-planning, CTS, place and route, RC extraction.
• Collaborate with front-end designers to achieve timing closure and optimize area/power.
• Perform physical verification (LVS/DRC/ERC/Antenna).
• Design ECO revisions and interface with foundry for tapeout activities.

Skills

Verilog HDL

VHDL design

Floor planning

Clock tree synthesis

Place and route

RC extraction

Timing ECO

Physical verification

Tapeout flow

USB connectivity

ASIC flow layout

Project management

Education

Electrical/Electronic Engineering degree

Tools

Siemens Calibre

Synopsys ICC2

Job description

FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED SINGAPORE BRANCH is seeking an experienced IC Physical Design Engineer to contribute to full-chip physical design development for FTDI products. You will work on tech file libraries, floor-planning, CTS, place and route, RC extraction and collaborate with front-end designers to meet timing closure.

The role requires a degree in Electrical/Electronic Engineering and 3+ years in ASIC flow layout design, with hands-on Verilog/VHDL experience and