SoC Timing Engineer: Closure, Power & Verification

Realtek Semiconductor Corp.; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Realtek Semiconductor Corp. in Singapore is seeking an ASIC Design Engineer to collaborate with system engineers on timing requirements, perform SoC timing closure, and optimize power structures.

The role includes formal verification work and supporting back-end timing violation analysis, scan insertion, and power optimization. The candidate should have a Bachelor's or Master’s degree in electronic engineering with ASIC design experience, familiar with ASIC flows, and strong UNIX/Linux scripting

Qualifications

• Bachelor’s or Master’s degree in electronic engineering (or equivalent) with ASIC design experience.
• Familiar with ASIC design flow.
• Experience in logic synthesis, static timing analysis, timing closure.
• Good understanding of DFT and power structure.
• Familiar with UNIX/Linux environment and scripting.
• Good communication and interpersonal skills.

Responsibilities

• Work with system engineers on timing requirements and feedback on optimization.
• Work on SoC timing constraint, synthesis and timing closure.
• Work on power structure, e.g. isolation of power domains, level-shifter crossing voltage domains.
• Conduct formal verification for release comparison.
• Support back-end implementation on timing violation analysis and fix.
• Support scan insertion and optimization.
• Support on power structure and power optimization.

Skills

ASIC design

Timing closure

Logic synthesis

Static timing analysis

DFT

Power structure

Communication skills

Education

Bachelor's or Master’s degree in Electronic Engineering

Tools

UNIX/Linux scripting

Job description

Realtek Semiconductor Corp. in Singapore is seeking an ASIC Design Engineer to collaborate with system engineers on timing requirements, perform SoC timing closure, and optimize power structures.

The role includes formal verification work and supporting back-end timing violation analysis, scan insertion, and power optimization. The candidate should have a Bachelor's or Master’s degree in electronic engineering with ASIC design experience, familiar with ASIC flows, and strong UNIX/Linux scripting