Digital Design Engineer - (Global Semicon / Ang Mo Kio / ASAP)

ADECCO PERSONNEL PTE LTD; Singapore; On-site; SGD 50,000 - 56,000; Full time

Benefits offered by this job

Completion Bonus

Job summary

ADECCO PERSONNEL PTE LTD in Singapore is seeking a Digital Design Engineer for a 12-month contract at Ang Mo Kio. Working hours are 9:00am to 6:00pm, Monday to Friday, with a completion bonus.

The role emphasizes IP and RTL design, verification, and architecture, requiring 1–3 years in semiconductor or high-tech R&D, with VHDL/Verilog and RTL skills. Salary ranges from 4,500 to 5,000 SGD monthly.

Qualifications

• Diploma or Degree in Engineering, Computer Engineering, Electrical or related studies.
• 1–3 years of relevant experience in semiconductor or high technology R&D.
• Experience in Hardware Design Language (VHDL / Verilog).
• Experience in digital design techniques and RTL coding.
• Architecture definition and design documentation experience.
• Lint, domain crossing, design for test, design for emulation experience.
• Scripting languages: Python, Perl, TCL.
• Experience with communication protocols (I2C, SPI, GPIO, UART).

Responsibilities

• Manage and handle IP and RTL design and verification.
• Handle IP and system architecture definition.
• Design and implementation documentation.
• Support functional verification and ensure 100% coverage.
• Ad hoc duties may be assigned.

Skills

VHDL / Verilog

RTL coding

Digital design

Architecture definition

Design for test

Design for emulation

Scripting (Python, Perl, TCL)

IP/RTL verification

I2C / SPI / GPIO / UART

Education

Diploma or Degree in Engineering / related field

Job description

The Opportunity

• Our client,Global Semiconductor industry
• Seeking forDigital Design Engineer
• Monday - Friday,9:00am to 6:00pm
• Working Location:Ang Mo Kio, Singapore
• Salary: $4500 - $5000
• Nearest MRT:Ang Mo Kio
• 12 months contract (renewable)
• Completion Bonus

The Talent

• Diploma or Degree in Engineering, Computer Engineering, Electrical or any related studies
• Min 1 to 3 years of relevantexperience in semiconductor or high technology R&D environment
• Experience in Hardware Design Language (VHDL / Verilog)
• Experience in Digital design techniques
• RTL coding
• Architecture definition
• Design and implementation specification
• Lint, domain crossing, design for test, design for emulation
• Scripting languages (Python, Perls, TCL)
• Experience with communication IPS (12C, 13C, SPI, GPIO and UART)

The Job

• Manage and handle IP and RTL Design and Verification
• Handle IP and System Architecture definition
• Design and implementation documentation
• Support functional verification and ensuring 100% coverage functionality are full covered
• Ad hoc duties will be assigned