Design Verification Manager

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD.; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. is seeking a Design Verification Manager to lead a driven verification team and drive state-of-the-art methodologies for complex SoC designs. You will oversee test plan reviews, plan execution, and strive for zero-defect results across massive verification spaces.

The role requires deep expertise in UVM, C/Python scripting, and strong leadership as you shape verification strategy and collaborate across IP blocks and system-level verification activities.

Qualifications

• Strong knowledge of SoC design principles, including IP block integration and system-level verification.
• Experience with test plan development, execution, and analysis.
• Familiarity with EDA tools and development flows for ASIC verification.
• High quality mindset and disciplined work ethic.
• Excellent team leadership and communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or scripting (Python/Perl).
• MSEE/BSEE in Electrical Engineering or Computer Engineering with at least 10 years of relevant experience.
• RTL design experience is a plus.
• Video processing and video analytics experience is a plus.

Responsibilities

• Lead a passionate verification team pushing the limits of design verification.
• Develop and deploy state-of-the-art verification methodologies for growing design complexities (UVM, C/C++ co-simulation, emulation, mixed-mode, formal).
• Conduct thorough test plan reviews and execute plans on time with high quality.
• Aim for zero-defect verification through rigorous strategy and execution.

Skills

UVM verification

Team leadership

Test plan

C/Python scripting

SoC principles

Communication

Education

MSEE/BSEE (Electrical/CE)

Tools

EDA tools

Job description

As a Design Verification Manager, you are expected to carry out the following responsibilities.

• Be in-charge of a passionate verification team that is constantly pushing the limits
• Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
• Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
• Achieve zero-defect, with the best and smartest approach to the large verification space.

Requirements

• Strong knowledge of SoC design principles, including IP block integration and system-level verification
• Experience with test plan development, execution, and analysis
• Familiarity with EDA tools and development flows for ASIC verification
• Highly disciplined, quality-minded, and highly driven for excellence.
• Excellent team leader and good communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or a scripting language such as python or perl.
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
• Experience in RTL design is a plus.
• Experience in video processing and video analytics is a plus.
• Passionate and strong in general programming is a plus.