Chip Physical Verification CAD Intern – Design & Automation

Mediatek Singapore Pte Ltd; Singapore; On-site; SGD 13,000 - 20,000; Part time

Job summary

Mediatek Singapore Pte Ltd is seeking a motivated student for hands-on experience in physical verification of chip tape-out. You will work with experienced engineers to learn DRC processes, layout tooling, and scripting to automate tasks. Mentors will guide you while you contribute to real-world tape-out activities.

The role emphasizes independent work, cross-team collaboration, and critical thinking as you gain exposure to full-chip construction and backend closure dynamics.

Qualifications

• Pursuing a degree in Electrical/Electronics/CS Engineering and able to work independently.
• Strong drive to learn and pick up new things in a fast-paced environment.
• Good communication and ability to collaborate across teams.
• Willingness to explore unfamiliar territory and seek innovative solutions.
• Demonstrated critical thinking when facing challenging problems.
• IC layout experience and scripting knowledge are a plus but not required.

Responsibilities

• Execute design rule checks on real chip design.
• Debug issues related to design rule checks during full chip integration.
• Do basic reporting on physical verification issues.
• Basic project management and project risk assessment reporting.
• Basic scripting automation to streamline workflows.

Skills

Cross-team collaboration

Independent work

Critical thinking

Communication

Learning mindset

Education

Pursuing Electrical/Electronics/CS Engineering degree

Tools

Laker

Calibre

Job description

Mediatek Singapore Pte Ltd is seeking a motivated student for hands-on experience in physical verification of chip tape-out. You will work with experienced engineers to learn DRC processes, layout tooling, and scripting to automate tasks. Mentors will guide you while you contribute to real-world tape-out activities.

The role emphasizes independent work, cross-team collaboration, and critical thinking as you gain exposure to full-chip construction and backend closure dynamics.