Senior/Staff Engineer, Design Implementation

BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD. seeks an experienced Synthesis Methodology Engineer to own RTL synthesis methodologies across AI SoC projects in Singapore. You will develop, maintain, and optimize synthesis flows, evaluate new EDA tools, and enable efficient implementation across technology nodes.

You will collaborate with Design, Backend, CAD, and EDA vendors to improve productivity and quality, while driving automation and robust sign-off workflows across multiple projects.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering.
• ≥5 years in ASIC/SoC RTL synthesis or synthesis methodology development.
• Hands-on with Synopsys Design Compiler.
• Familiarity with sign-off tools: PrimeTime, Formality, VC SpyGlass, VCLP.
• Experience with RTL synthesis, timing optimization, and ASIC implementation flow.
• Proficiency in Tcl, Shell, or Python scripting.
• Experience evaluating or deploying Fusion Compiler or Cadence Genus.
• Strong analytical, debugging, and problem-solving skills.
• Strong communication across cross-functional teams.

Responsibilities

• Synthesize and optimize RTL flows using Design Compiler for ASIC/AI SoC.
• Design and improve synthesis methodologies, automation, and reusable workflows.
• Perform RTL synthesis for AI/NPU blocks ensuring quality and timing convergence.
• Develop sign-off methodologies with PrimeTime, Formality, SpyGlass, and VCLP.
• Support technology node migrations, library updates, and flow enhancements.
• Evaluate and deploy new EDA tools such as Fusion Compiler and Genus.
• Develop automation scripts to boost synthesis productivity and flow robustness.
• Collaborate with RTL, Backend, CAD and EDA vendors to resolve issues.

Skills

Analytical thinking

Problem solving

Communication

Debugging

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

PrimeTime

Formality

VC SpyGlass

VCLP

Fusion Compiler

Cadence Genus

Tcl scripting

Shell scripting

Python scripting

Job description

Position Overview:

We are looking for an experienced Synthesis Methodology Engineer to own and drive RTL synthesis methodologies across our AI SoC development projects. You will be responsible for developing, maintaining, and optimizing synthesis flows, evaluating new EDA tools, and enabling efficient implementation across multiple technology nodes.

You will collaborate closely with Design, Backend, CAD, and EDA vendors to improve design productivity and quality.

Responsibilities:

• Synthesis Flow Ownership:Develop, maintain, and optimize RTL synthesis flows using Synopsys Design Compiler to support ASIC/AI SoC development.
• Synthesis Methodology:Design and improve synthesis methodologies, automation, and reusable workflows across multiple projects and technology nodes.
• RTL Synthesis:Perform RTL synthesis for AI/NPU-related blocks while ensuring quality, performance, and design convergence.
• Sign-off Verification:Develop and maintain sign-off methodologies using PrimeTime, Formality, VC SpyGlass, and VCLP to ensure design integrity.
• Technology Migration:Support technology node migration, library updates, and flow enhancements to meet evolving project requirements.
• EDA Tool Evaluation: Evaluate, validate, and deploy new EDA tools and methodologies such as Synopsys Fusion Compiler and Cadence Genus.
• Automation & Scripting:Develop scripts and automation to improve synthesis productivity, flow robustness, and engineering efficiency.
• Cross-functional Collaboration:Work closely with RTL designers, Backend, CAD, and EDA vendors to resolve synthesis, timing, and methodology issues.

Qualification/ Requirements:

• Education:Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Minimum5 yearsof experience in ASIC/SoC RTL synthesis or synthesis methodology development.
• Strong hands-on experience withSynopsys Design Compiler.
• Familiarity with sign-off tools such asPrimeTime, Formality, VC SpyGlass,andVCLP.
• Experience with RTL synthesis, timing optimization, synthesis constraints, and ASIC implementation flow.
• Proficiency inTcl, Shell, or Pythonscripting for automation and flow development.
• Experience evaluating or deploying EDA tools such asFusion CompilerorCadence Genusis highly preferred.
• Strong analytical, debugging, and problem-solving skills.
• Good communication skills with the ability to collaborate effectively across cross-functional engineering teams.